[PATCH] D127721: [RISCV][NFC] Add load/store instructions in rv64*-invalid.s
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Tue Jun 14 23:19:35 PDT 2022
Pretty-box marked 6 inline comments as done.
Pretty-box added inline comments.
================
Comment at: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s:4
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
----------------
benshi001 wrote:
> I guess you want `flh`/`fsh` ?
Modified RUN line -mattr
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D127721/new/
https://reviews.llvm.org/D127721
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