[PATCH] D127475: [RISCV][NFC] precommit tests for D127474
Ben Shi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 14 20:48:54 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa0af0496147d: [RISCV][NFC] Add more tests for instruction selection of 'mul' (authored by Pretty-box, committed by benshi001).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D127475/new/
https://reviews.llvm.org/D127475
Files:
llvm/test/CodeGen/RISCV/mul.ll
Index: llvm/test/CodeGen/RISCV/mul.ll
===================================================================
--- llvm/test/CodeGen/RISCV/mul.ll
+++ llvm/test/CodeGen/RISCV/mul.ll
@@ -1580,3 +1580,55 @@
%r = and i8 %a, 15
ret i8 %r
}
+
+define i8 @mulsub_demand(i8 %x, i8 %y) nounwind {
+; RV32I-LABEL: mulsub_demand:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: li a1, 14
+; RV32I-NEXT: call __mulsi3 at plt
+; RV32I-NEXT: sub a0, s0, a0
+; RV32I-NEXT: andi a0, a0, 15
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: mulsub_demand:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a2, 14
+; RV32IM-NEXT: mul a0, a0, a2
+; RV32IM-NEXT: sub a0, a1, a0
+; RV32IM-NEXT: andi a0, a0, 15
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: mulsub_demand:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: li a1, 14
+; RV64I-NEXT: call __muldi3 at plt
+; RV64I-NEXT: subw a0, s0, a0
+; RV64I-NEXT: andi a0, a0, 15
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: mulsub_demand:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a2, 14
+; RV64IM-NEXT: mulw a0, a0, a2
+; RV64IM-NEXT: subw a0, a1, a0
+; RV64IM-NEXT: andi a0, a0, 15
+; RV64IM-NEXT: ret
+ %m = mul i8 %x, 14
+ %a = sub i8 %y, %m
+ %r = and i8 %a, 15
+ ret i8 %r
+}
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