[llvm] facb965 - [RISCV] Minor code/comment improvement in prepass of InsertVSETVLI [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-06-14T16:18:11-07:00
New Revision: facb96584eebd87eaedc99b3e44dac86ae1bab29

URL: https://github.com/llvm/llvm-project/commit/facb96584eebd87eaedc99b3e44dac86ae1bab29
DIFF: https://github.com/llvm/llvm-project/commit/facb96584eebd87eaedc99b3e44dac86ae1bab29.diff

LOG: [RISCV] Minor code/comment improvement in prepass of InsertVSETVLI [nfc]

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index e7c8d6eda641..c86dfa080b70 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1213,17 +1213,22 @@ void RISCVInsertVSETVLI::doLocalPrepass(MachineBasicBlock &MBB) {
     if (RISCVII::hasSEWOp(TSFlags)) {
       if (RISCVII::hasVLOp(TSFlags)) {
         const auto Require = computeInfoForInstr(MI, TSFlags, MRI);
-        // If the AVL is the result of a previous vsetvli which has the
-        // same AVL and VLMAX as our current state, we can reuse the AVL
-        // from the current state for the new one.  This allows us to
-        // generate 'vsetvli x0, x0, vtype" or possible skip the transition
-        // entirely.
-        if (!CurInfo.isUnknown() && Require.hasAVLReg() &&
-            Require.getAVLReg().isVirtual()) {
+        // Two cases involving an AVL resulting from a previous vsetvli.
+        // 1) If the AVL is the result of a previous vsetvli which has the
+        //    same AVL and VLMAX as our current state, we can reuse the AVL
+        //    from the current state for the new one.  This allows us to
+        //    generate 'vsetvli x0, x0, vtype" or possible skip the transition
+        //    entirely.
+        // 2) If AVL is defined by a vsetvli with the same VLMAX, we can
+        //    replace the AVL operand with the AVL of the defining vsetvli.
+        //    We avoid general register AVLs to avoid extending live ranges
+        //    without being sure we can kill the original source reg entirely.
+        if (Require.hasAVLReg() && Require.getAVLReg().isVirtual()) {
           if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
             if (isVectorConfigInstr(*DefMI)) {
               VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
-              if (DefInfo.hasSameAVL(CurInfo) &&
+              // case 1
+              if (!CurInfo.isUnknown() && DefInfo.hasSameAVL(CurInfo) &&
                   DefInfo.hasSameVLMAX(CurInfo)) {
                 MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
                 if (CurInfo.hasAVLImm())
@@ -1235,19 +1240,7 @@ void RISCVInsertVSETVLI::doLocalPrepass(MachineBasicBlock &MBB) {
                 CurInfo = computeInfoForInstr(MI, TSFlags, MRI);
                 continue;
               }
-            }
-          }
-        }
-
-        // If AVL is defined by a vsetvli with the same VLMAX, we can
-        // replace the AVL operand with the AVL of the defining vsetvli.
-        // We avoid general register AVLs to avoid extending live ranges
-        // without being sure we can kill the original source reg entirely.
-        // TODO: We can ignore policy bits here, we only need VL to be the same.
-        if (Require.hasAVLReg() && Require.getAVLReg().isVirtual()) {
-          if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
-            if (isVectorConfigInstr(*DefMI)) {
-              VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+              // case 2
               if (DefInfo.hasSameVLMAX(Require) &&
                   (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
                 MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));