[PATCH] D125836: [DAG] Fold (srl (shl x, c1), c2) -> and(shl/srl(x, c3), m) (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9442
+      SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff);
+      return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift, Mask);
+    }
----------------
RKSimon wrote:
> craig.topper wrote:
> > RKSimon wrote:
> > > craig.topper wrote:
> > > > Why is the last SDLoc from N0?
> > > It was copy+pasted from the (shl (srl x, c1), c2) variant
> > Is that correct? Can you swap the order of debug locs? The N0 debug loc is now after the N location in the DAG
> I'll take a look
D127772


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  https://reviews.llvm.org/D125836/new/

https://reviews.llvm.org/D125836