[PATCH] D125836: [DAG] Fold (srl (shl x, c1), c2) -> and(shl/srl(x, c3), m) (WIP)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9442
+      SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff);
+      return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift, Mask);
+    }
----------------
Why is the last SDLoc from N0?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125836/new/

https://reviews.llvm.org/D125836