[PATCH] D127727: [RISCV] Turn on SeparateConstOffsetFromGEPPass for RISC-V target and added optional modification strategy in it

[Elena Lepilkina via Phabricator via llvm-commits]

eklepilkina added a comment.

Sorry, I had to provide the context at the beginning.

Now clang for RISC-V doesn't use offset addressing in generated assembly. Example from Dhrystone

   addiw   a0, s1, 5
   slli    a1, a0, 0x2
   add     a2, s4, a1
   sw      s2, 0(a2)
   addiw   a3, s1, 6
   slli    a3, a3, 0x2
   add     a3, a3, s4
   sw      s2, 0(a3)
   addiw   a3, s1, 35
   slli    a3, a3, 0x2
  add     a3, a3, s4
  sw      a0, 0(a3)

It's inefficient because we can use offsets.
Adding this pass allows to generate the next code

      addiw   a4, a2, 5
      slli    a5, a2, 2
      add a0, a0, a5
      sw  a3, 20(a0)
      sw  a3, 24(a0)
      sw  a4, 140(a0)
  ...

`SeparateConstOffsetFromGEPPass` is used to solve this problem in targets with limited addressing modes.
The changes inside pass was made because modification of all GEPs isn't profitable, seems that we need at least 2 GEPs and one value that was used for index that can be removed after modification. Otherwise we don't decrease register pressure.


Repository:
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https://reviews.llvm.org/D127727