[llvm] 0cb3355 - [AArch64][NFC] Fix a comment error

[via llvm-commits]

Author: zhongyunde
Date: 2022-06-14T13:57:41+08:00
New Revision: 0cb33551ecd6ac2ea0056c33a5dc6f6b47bc4306

URL: https://github.com/llvm/llvm-project/commit/0cb33551ecd6ac2ea0056c33a5dc6f6b47bc4306
DIFF: https://github.com/llvm/llvm-project/commit/0cb33551ecd6ac2ea0056c33a5dc6f6b47bc4306.diff

LOG: [AArch64][NFC] Fix a comment error

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D127708

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64.td
    llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 8d5bf16a9a654..42542611b4abe 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -217,7 +217,7 @@ def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
 
 def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address",
     "IsStoreAddressAscend", "false",
-    "Schedule scalar stores by ascending address">;
+    "Schedule vector stores by ascending address">;
 
 def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow",
     "true", "STR of Q register with register offset is slow">;

diff  --git a/llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp b/llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp
index 9c69a3704548a..6c8845ee85986 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp
@@ -26,7 +26,7 @@ static bool needReorderStoreMI(const MachineInstr *MI) {
        return false;
     LLVM_FALLTHROUGH;
   case AArch64::STPQi:
-    return AArch64InstrInfo::getLdStOffsetOp(*MI).getType() == MachineOperand::MO_Immediate;
+    return AArch64InstrInfo::getLdStOffsetOp(*MI).isImm();
   }
 
   return false;