[PATCH] D124926: [LoopInterchange] New cost model for loop interchange

[Congzhe Cao via Phabricator via llvm-commits]

congzhe added a comment.

Based on the discussion in the Discourse (https://discourse.llvm.org/t/rfc-targettransforminfo-add-an-option-to-supply-cache-line-size-if-not-provided-by-the-target/63114) and D127342 <https://reviews.llvm.org/D127342>, I'm thinking that there might be two ways to move forward.

1. We can modify `TargetTransformInfo.cpp` in D127342 <https://reviews.llvm.org/D127342> as follows, and pass "-cache-line-size=64" to the RUN lines for loop interchange test.  Since as pointed out in the Discourse, some embedded devices have no cache so we could not default the cache line size to 64 in `TargetTransformInfo.cpp`. Moreover, loop interchange is a mid-end pass anyways so it might be difficult to take each backend target into account, we might just want to pass "-cache-line-size=64" as a general setup to ensure it works as expected in the mid-end.

  unsigned TargetTransformInfo::getCacheLineSize() const {
    return CacheLineSize.getNumOccurrences() > 0 
               ? CacheLineSize
               : TTIImpl->getCacheLineSize();
  }



2. We could mimic the tests in loop date prefetch, where the tests do depend on specific backend targets, and are put under different directories, i.e., `test/Transforms/LoopDataPrefetch/AArch64/large-stride.ll`, `test/Transforms/LoopDataPrefetch/PowerPC/basic.ll`.

I'm wondering if you think any of the two approaches make sense? @bmahjour


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  https://reviews.llvm.org/D124926/new/

https://reviews.llvm.org/D124926