[PATCH] D127603: [AArch64] isSeveralBitsExtractOpFromShr - match UBFM patterns with value tracking (RFC)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1958
   // Value2 = AND Value, MaskImm
   // SRL Value2, ShiftImm
   //
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The pattern we're looking for is SRL+AND.  The modified version of the function doesn't explicitly check for the "AND" operation at all.  I guess you can describe "AND" as "an operation with known zero bits in the result, and can be eliminated by SimplifyMultipleUseDemandedBits", but that seems like an awfully confusing description.

How does this change actually generalize the matching in practice?  Are we just looking for different AND masks, or can we actually match operations which aren't AND?

Maybe it would make the result easier to read if we extract the code that checks for the masking operation into a separate "MatchMaskOperation" function?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127603/new/

https://reviews.llvm.org/D127603