[PATCH] D127701: [docs] Minor fixes to CodeGenerator docs

[Youngsuk Kim via Phabricator via llvm-commits]

JOE1994 created this revision.
JOE1994 added reviewers: myhsu, spatel, DanielMcIntosh-IBM.
Herald added a project: All.
JOE1994 requested review of this revision.
Herald added a project: LLVM.

- Fix incorrect word usage: commutable => commutative
- Other changes are grammar fixes and minor improvements in phrasing


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127701

Files:
  llvm/docs/CodeGenerator.rst


Index: llvm/docs/CodeGenerator.rst
===================================================================
--- llvm/docs/CodeGenerator.rst
+++ llvm/docs/CodeGenerator.rst
@@ -288,7 +288,7 @@
 supported by the target.  Descriptions define things like the mnemonic for
 the opcode, the number of operands, the list of implicit register uses and defs,
 whether the instruction has certain target-independent properties (accesses
-memory, is commutable, etc), and holds any target-specific flags.
+memory, is commutative, etc), and holds any target-specific flags.
 
 The ``TargetFrameLowering`` class
 ---------------------------------
@@ -419,7 +419,7 @@
 of fixed registers.  In particular, there are often places in the instruction
 stream where the register allocator *must* arrange for a particular value to be
 in a particular register.  This can occur due to limitations of the instruction
-set (e.g., the X86 can only do a 32-bit divide with the ``EAX``/``EDX``
+set (e.g., the X86 can do a 32-bit divide with only the ``EAX``/``EDX``
 registers), or external factors like calling conventions.  In any case, the
 instruction selector should emit code that copies a virtual register into or out
 of a physical register when needed.
@@ -582,7 +582,7 @@
 Packing / bundling of MachineInstrs for VLIW architectures should
 generally be done as part of the register allocation super-pass. More
 specifically, the pass which determines what MIs should be bundled
-together should be done after code generator exits SSA form
+together should be run after code generator exits SSA form
 (i.e. after two-address pass, PHI elimination, and copy coalescing).
 Such bundles should be finalized (i.e. adding BUNDLE MIs and input and
 output register MachineOperands) after virtual registers have been
@@ -606,7 +606,7 @@
 llvm-mc tool to implement standalone machine code assemblers and disassemblers.
 
 This section describes some of the important classes.  There are also a number
-of important subsystems that interact at this layer, they are described later in
+of important subsystems that interact at this layer, which are described later in
 this manual.
 
 .. _MCStreamer:
@@ -616,7 +616,7 @@
 
 MCStreamer is best thought of as an assembler API.  It is an abstract API which
 is *implemented* in different ways (e.g. to output a .s file, output an ELF .o
-file, etc) but whose API correspond directly to what you see in a .s file.
+file, etc) but whose API corresponds directly to what you see in a .s file.
 MCStreamer has one method per directive, such as EmitLabel, EmitSymbolAttribute,
 switchSection, emitValue (for .byte, .word), etc, which directly correspond to
 assembly level directives.  It also has an EmitInstruction method, which is used
@@ -1037,7 +1037,7 @@
 for your target.  It has the following strengths:
 
 * At compiler-compile time, it analyzes your instruction patterns and tells you
-  if your patterns make sense or not.
+  whether your patterns make sense or not.
 
 * It can handle arbitrary constraints on operands for the pattern match.  In
   particular, it is straight-forward to say things like "match any immediate
@@ -1105,7 +1105,7 @@
   express.
 
 While it has many strengths, the system currently has some limitations,
-primarily because it is a work in progress and is not yet finished:
+primarily because it is a work in progress:
 
 * Overall, there is no way to define or match SelectionDAG nodes that define
   multiple values (e.g. ``SMUL_LOHI``, ``LOAD``, ``CALL``, etc).  This is the


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