[llvm] 438c312 - [AMDGPU] Add GFX11 flat scratch test coverage
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 13 05:38:17 PDT 2022
Author: Jay Foad
Date: 2022-06-13T13:38:12+01:00
New Revision: 438c312c039a2ca1976d6a9e8389387d2e7a73ce
URL: https://github.com/llvm/llvm-project/commit/438c312c039a2ca1976d6a9e8389387d2e7a73ce
DIFF: https://github.com/llvm/llvm-project/commit/438c312c039a2ca1976d6a9e8389387d2e7a73ce.diff
LOG: [AMDGPU] Add GFX11 flat scratch test coverage
Added:
Modified:
llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
llvm/test/CodeGen/AMDGPU/flat-scratch.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
index c0fa2ce737984..3dd8dcf0c09f6 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx940 < %s | FileCheck %s -check-prefixes=GFX940-SDAG
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx940 < %s | FileCheck %s -check-prefixes=GFX940-GISEL
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11-SDAG
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11-GISEL
; Test flat scratch SVS addressing mode with various combinations of alignment
; of soffset, voffset and inst_offset.
@@ -41,6 +43,39 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff1_voff1:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff1_voff1:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff1 = mul i32 %soff, 1
%a = alloca i8, i32 64, align 4, addrspace(5)
@@ -93,6 +128,41 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff1_voff2:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff1_voff2:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff1 = mul i32 %soff, 1
%a = alloca i8, i32 64, align 4, addrspace(5)
@@ -145,6 +215,41 @@ define amdgpu_kernel void @soff1_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff1_voff4:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff1_voff4:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff1 = mul i32 %soff, 1
%a = alloca i8, i32 64, align 4, addrspace(5)
@@ -197,6 +302,41 @@ define amdgpu_kernel void @soff2_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff2_voff1:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff2_voff1:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff2 = mul i32 %soff, 2
%a = alloca i8, i32 64, align 4, addrspace(5)
@@ -251,6 +391,43 @@ define amdgpu_kernel void @soff2_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff2_voff2:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff2_voff2:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff2 = mul i32 %soff, 2
%a = alloca i8, i32 64, align 4, addrspace(5)
@@ -305,6 +482,43 @@ define amdgpu_kernel void @soff2_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff2_voff4:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff2_voff4:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff2 = mul i32 %soff, 2
%a = alloca i8, i32 64, align 4, addrspace(5)
@@ -357,6 +571,41 @@ define amdgpu_kernel void @soff4_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff4_voff1:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff4_voff1:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff4 = mul i32 %soff, 4
%a = alloca i8, i32 64, align 4, addrspace(5)
@@ -411,6 +660,43 @@ define amdgpu_kernel void @soff4_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff4_voff2:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff4_voff2:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff4 = mul i32 %soff, 4
%a = alloca i8, i32 64, align 4, addrspace(5)
@@ -465,6 +751,43 @@ define amdgpu_kernel void @soff4_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
+;
+; GFX11-SDAG-LABEL: soff4_voff4:
+; GFX11-SDAG: ; %bb.0: ; %bb
+; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
+; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: soff4_voff4:
+; GFX11-GISEL: ; %bb.0: ; %bb
+; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff4 = mul i32 %soff, 4
%a = alloca i8, i32 64, align 4, addrspace(5)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
index 95e809711e481..a8e97b5f7f49a 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
@@ -1,10 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx1030 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11 %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9-PAL %s
; RUN: llc -march=amdgcn -mcpu=gfx940 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX940 %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-PAL,GFX1010-PAL %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1030 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-PAL,GFX1030-PAL %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11-PAL %s
define amdgpu_kernel void @zero_init_kernel() {
; GFX9-LABEL: zero_init_kernel:
@@ -49,6 +51,23 @@ define amdgpu_kernel void @zero_init_kernel() {
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:16
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: zero_init_kernel:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: s_mov_b32 s1, s0
+; GFX11-NEXT: s_mov_b32 s2, s0
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:64
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:48
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:32
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:16
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: zero_init_kernel:
; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -146,6 +165,23 @@ define amdgpu_kernel void @zero_init_kernel() {
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:32
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:16
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: zero_init_kernel:
+; GFX11-PAL: ; %bb.0:
+; GFX11-PAL-NEXT: s_mov_b32 s0, 0
+; GFX11-PAL-NEXT: s_mov_b32 s1, s0
+; GFX11-PAL-NEXT: s_mov_b32 s2, s0
+; GFX11-PAL-NEXT: s_mov_b32 s3, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-PAL-NEXT: s_clause 0x3
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:64
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:48
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:32
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:16
+; GFX11-PAL-NEXT: s_endpgm
%alloca = alloca [32 x i16], align 2, addrspace(5)
%cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)*
call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)
@@ -190,6 +226,26 @@ define void @zero_init_foo() {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: zero_init_foo:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: s_mov_b32 s1, s0
+; GFX11-NEXT: s_mov_b32 s2, s0
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 offset:48
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 offset:32
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 offset:16
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: zero_init_foo:
; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -242,6 +298,26 @@ define void @zero_init_foo() {
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: zero_init_foo:
+; GFX11-PAL: ; %bb.0:
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: s_mov_b32 s0, 0
+; GFX11-PAL-NEXT: s_mov_b32 s1, s0
+; GFX11-PAL-NEXT: s_mov_b32 s2, s0
+; GFX11-PAL-NEXT: s_mov_b32 s3, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-PAL-NEXT: s_clause 0x3
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s32 offset:48
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s32 offset:32
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s32 offset:16
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s32
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: zero_init_foo:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -302,6 +378,22 @@ define amdgpu_kernel void @store_load_sindex_kernel(i32 %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_sindex_kernel:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s1, s0, 15
+; GFX11-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-NEXT: s_add_i32 s0, s0, 4
+; GFX11-NEXT: s_add_i32 s1, s1, 4
+; GFX11-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_sindex_kernel:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[4:5]
@@ -364,6 +456,22 @@ define amdgpu_kernel void @store_load_sindex_kernel(i32 %idx) {
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_sindex_kernel:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_load_b32 s0, s[0:1], 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-PAL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PAL-NEXT: s_and_b32 s1, s0, 15
+; GFX11-PAL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-PAL-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-PAL-NEXT: s_add_i32 s0, s0, 4
+; GFX11-PAL-NEXT: s_add_i32 s1, s1, 4
+; GFX11-PAL-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
; GCN-LABEL: store_load_sindex_kernel:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
@@ -427,6 +535,20 @@ define amdgpu_ps void @store_load_sindex_foo(i32 inreg %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_sindex_foo:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-NEXT: s_and_b32 s1, s0, 15
+; GFX11-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-NEXT: s_add_i32 s0, s0, 4
+; GFX11-NEXT: s_add_i32 s1, s1, 4
+; GFX11-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_sindex_foo:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -484,6 +606,20 @@ define amdgpu_ps void @store_load_sindex_foo(i32 inreg %idx) {
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_sindex_foo:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-PAL-NEXT: s_and_b32 s1, s0, 15
+; GFX11-PAL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-PAL-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-PAL-NEXT: s_add_i32 s0, s0, 4
+; GFX11-PAL-NEXT: s_add_i32 s1, s1, 4
+; GFX11-PAL-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
; GCN-LABEL: store_load_sindex_foo:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_lshl_b32 s1, s0, 2
@@ -541,6 +677,17 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_vindex_kernel:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 4, v0
+; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:4 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_vindex_kernel:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -591,6 +738,17 @@ define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_vindex_kernel:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v2, 4, v0
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:4 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
; GCN-LABEL: store_load_vindex_kernel:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -645,6 +803,20 @@ define void @store_load_vindex_foo(i32 %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_vindex_foo:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_and_b32_e32 v1, 15, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
+; GFX11-NEXT: scratch_store_b32 v0, v2, s32 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, v1, s32 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_vindex_foo:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -685,6 +857,20 @@ define void @store_load_vindex_foo(i32 %idx) {
; GFX10-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_vindex_foo:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_and_b32_e32 v1, 15, v0
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v1, 2, v1
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v2, s32 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, s32 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: store_load_vindex_foo:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -728,6 +914,15 @@ define void @private_ptr_foo(float addrspace(5)* nocapture %arg) {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: private_ptr_foo:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0x41200000
+; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:4
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: private_ptr_foo:
; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -752,6 +947,15 @@ define void @private_ptr_foo(float addrspace(5)* nocapture %arg) {
; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off offset:4
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: private_ptr_foo:
+; GFX11-PAL: ; %bb.0:
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 0x41200000
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:4
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: private_ptr_foo:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -812,6 +1016,25 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:320
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: zero_init_small_offset_kernel:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: s_mov_b32 s1, s0
+; GFX11-NEXT: s_mov_b32 s2, s0
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:272
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:288
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:304
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:320
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: zero_init_small_offset_kernel:
; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -919,6 +1142,25 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:304
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:320
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: zero_init_small_offset_kernel:
+; GFX11-PAL: ; %bb.0:
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_mov_b32 s0, 0
+; GFX11-PAL-NEXT: s_mov_b32 s1, s0
+; GFX11-PAL-NEXT: s_mov_b32 s2, s0
+; GFX11-PAL-NEXT: s_mov_b32 s3, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-PAL-NEXT: s_clause 0x3
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:272
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:288
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:304
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:320
+; GFX11-PAL-NEXT: s_endpgm
%padding = alloca [64 x i32], align 4, addrspace(5)
%alloca = alloca [32 x i16], align 2, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
@@ -970,6 +1212,28 @@ define void @zero_init_small_offset_foo() {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: zero_init_small_offset_foo:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, off, s32 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: s_mov_b32 s1, s0
+; GFX11-NEXT: s_mov_b32 s2, s0
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 offset:256
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 offset:272
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 offset:288
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 offset:304
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: zero_init_small_offset_foo:
; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1028,6 +1292,28 @@ define void @zero_init_small_offset_foo() {
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: zero_init_small_offset_foo:
+; GFX11-PAL: ; %bb.0:
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s32 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_mov_b32 s0, 0
+; GFX11-PAL-NEXT: s_mov_b32 s1, s0
+; GFX11-PAL-NEXT: s_mov_b32 s2, s0
+; GFX11-PAL-NEXT: s_mov_b32 s3, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-PAL-NEXT: s_clause 0x3
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s32 offset:256
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s32 offset:272
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s32 offset:288
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s32 offset:304
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: zero_init_small_offset_foo:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1097,6 +1383,24 @@ define amdgpu_kernel void @store_load_sindex_small_offset_kernel(i32 %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_sindex_small_offset_kernel:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s1, s0, 15
+; GFX11-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-NEXT: s_addk_i32 s0, 0x104
+; GFX11-NEXT: s_addk_i32 s1, 0x104
+; GFX11-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_sindex_small_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[4:5]
@@ -1194,6 +1498,24 @@ define amdgpu_kernel void @store_load_sindex_small_offset_kernel(i32 %idx) {
; GFX1030-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_sindex_small_offset_kernel:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_load_b32 s0, s[0:1], 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-PAL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PAL-NEXT: s_and_b32 s1, s0, 15
+; GFX11-PAL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-PAL-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-PAL-NEXT: s_addk_i32 s0, 0x104
+; GFX11-PAL-NEXT: s_addk_i32 s1, 0x104
+; GFX11-PAL-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
bb:
%padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5)
@@ -1250,6 +1572,22 @@ define amdgpu_ps void @store_load_sindex_small_offset_foo(i32 inreg %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_sindex_small_offset_foo:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-NEXT: s_and_b32 s1, s0, 15
+; GFX11-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-NEXT: s_addk_i32 s0, 0x104
+; GFX11-NEXT: s_addk_i32 s1, 0x104
+; GFX11-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_sindex_small_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -1340,6 +1678,22 @@ define amdgpu_ps void @store_load_sindex_small_offset_foo(i32 inreg %idx) {
; GFX1030-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_sindex_small_offset_foo:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-PAL-NEXT: s_and_b32 s1, s0, 15
+; GFX11-PAL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-PAL-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-PAL-NEXT: s_addk_i32 s0, 0x104
+; GFX11-PAL-NEXT: s_addk_i32 s1, 0x104
+; GFX11-PAL-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
bb:
%padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5)
@@ -1392,6 +1746,19 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_vindex_small_offset_kernel:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 0x104, v0
+; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:260 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_vindex_small_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -1473,6 +1840,19 @@ define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX1030-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_vindex_small_offset_kernel:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-PAL-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v2, 0x104, v0
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:260 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
bb:
%padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5)
@@ -1527,6 +1907,22 @@ define void @store_load_vindex_small_offset_foo(i32 %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_vindex_small_offset_foo:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_and_b32_e32 v1, 15, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-NEXT: scratch_load_b32 v3, off, s32 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
+; GFX11-NEXT: scratch_store_b32 v0, v2, s32 offset:256 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, v1, s32 offset:256 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_vindex_small_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1576,6 +1972,22 @@ define void @store_load_vindex_small_offset_foo(i32 %idx) {
; GFX10-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_vindex_small_offset_foo:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_and_b32_e32 v1, 15, v0
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-PAL-NEXT: scratch_load_b32 v3, off, s32 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v1, 2, v1
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v2, s32 offset:256 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, s32 offset:256 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: store_load_vindex_small_offset_foo:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1658,6 +2070,28 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: zero_init_large_offset_kernel:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: scratch_load_b32 v0, off, off offset:16 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4010
+; GFX11-NEXT: s_mov_b32 s1, s0
+; GFX11-NEXT: s_mov_b32 s2, s0
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo
+; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4010
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:16
+; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4010
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:32
+; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4010
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:48
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: zero_init_large_offset_kernel:
; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -1773,6 +2207,28 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
; GFX1030-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: zero_init_large_offset_kernel:
+; GFX11-PAL: ; %bb.0:
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, off offset:16 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_mov_b32 s0, 0
+; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010
+; GFX11-PAL-NEXT: s_mov_b32 s1, s0
+; GFX11-PAL-NEXT: s_mov_b32 s2, s0
+; GFX11-PAL-NEXT: s_mov_b32 s3, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo
+; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:16
+; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:32
+; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:48
+; GFX11-PAL-NEXT: s_endpgm
%padding = alloca [4096 x i32], align 4, addrspace(5)
%alloca = alloca [32 x i16], align 2, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
@@ -1832,6 +2288,31 @@ define void @zero_init_large_offset_foo() {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: zero_init_large_offset_foo:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:16 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4010
+; GFX11-NEXT: s_mov_b32 s1, s0
+; GFX11-NEXT: s_mov_b32 s2, s0
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo
+; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4010
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:16
+; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4010
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:32
+; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4010
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:48
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: zero_init_large_offset_foo:
; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1930,6 +2411,31 @@ define void @zero_init_large_offset_foo() {
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1030-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: zero_init_large_offset_foo:
+; GFX11-PAL: ; %bb.0:
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s32 offset:16 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_mov_b32 s0, 0
+; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4010
+; GFX11-PAL-NEXT: s_mov_b32 s1, s0
+; GFX11-PAL-NEXT: s_mov_b32 s2, s0
+; GFX11-PAL-NEXT: s_mov_b32 s3, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo
+; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4010
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:16
+; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4010
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:32
+; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4010
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:48
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
%padding = alloca [4096 x i32], align 4, addrspace(5)
%alloca = alloca [32 x i16], align 2, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
@@ -1982,6 +2488,24 @@ define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_sindex_large_offset_kernel:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s1, s0, 15
+; GFX11-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-NEXT: s_addk_i32 s0, 0x4004
+; GFX11-NEXT: s_addk_i32 s1, 0x4004
+; GFX11-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_sindex_large_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[4:5]
@@ -2079,6 +2603,24 @@ define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) {
; GFX1030-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_sindex_large_offset_kernel:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_load_b32 s0, s[0:1], 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-PAL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PAL-NEXT: s_and_b32 s1, s0, 15
+; GFX11-PAL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-PAL-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-PAL-NEXT: s_addk_i32 s0, 0x4004
+; GFX11-PAL-NEXT: s_addk_i32 s1, 0x4004
+; GFX11-PAL-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
bb:
%padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5)
@@ -2135,6 +2677,22 @@ define amdgpu_ps void @store_load_sindex_large_offset_foo(i32 inreg %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_sindex_large_offset_foo:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-NEXT: s_and_b32 s1, s0, 15
+; GFX11-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-NEXT: s_addk_i32 s0, 0x4004
+; GFX11-NEXT: s_addk_i32 s1, 0x4004
+; GFX11-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_sindex_large_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -2225,6 +2783,22 @@ define amdgpu_ps void @store_load_sindex_large_offset_foo(i32 inreg %idx) {
; GFX1030-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_sindex_large_offset_foo:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, off offset:4 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 15
+; GFX11-PAL-NEXT: s_and_b32 s1, s0, 15
+; GFX11-PAL-NEXT: s_lshl_b32 s0, s0, 2
+; GFX11-PAL-NEXT: s_lshl_b32 s1, s1, 2
+; GFX11-PAL-NEXT: s_addk_i32 s0, 0x4004
+; GFX11-PAL-NEXT: s_addk_i32 s1, 0x4004
+; GFX11-PAL-NEXT: scratch_store_b32 off, v0, s0 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s1 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
bb:
%padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5)
@@ -2277,6 +2851,20 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_vindex_large_offset_kernel:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4004
+; GFX11-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 0x4004, v0
+; GFX11-NEXT: scratch_store_b32 v0, v1, vcc_lo dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_vindex_large_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -2359,6 +2947,20 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX1030-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_vindex_large_offset_kernel:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
+; GFX11-PAL-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_sub_nc_u32_e32 v2, 0x4004, v0
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, vcc_lo dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v2, off offset:124 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
bb:
%padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5)
@@ -2413,6 +3015,24 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_vindex_large_offset_foo:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_and_b32_e32 v1, 15, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
+; GFX11-NEXT: scratch_load_b32 v3, off, s32 offset:4 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
+; GFX11-NEXT: scratch_store_b32 v0, v2, vcc_lo dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
+; GFX11-NEXT: scratch_load_b32 v0, v1, vcc_lo glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_vindex_large_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2464,6 +3084,24 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
; GFX10-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_vindex_large_offset_foo:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_and_b32_e32 v1, 15, v0
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
+; GFX11-PAL-NEXT: scratch_load_b32 v3, off, s32 offset:4 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v1, 2, v1
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v2, vcc_lo dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, vcc_lo glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: store_load_vindex_large_offset_foo:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2532,6 +3170,19 @@ define amdgpu_kernel void @store_load_large_imm_offset_kernel() {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_large_imm_offset_kernel:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: v_mov_b32_e32 v0, 13
+; GFX11-NEXT: v_mov_b32_e32 v1, 0x3000
+; GFX11-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-NEXT: scratch_store_b32 off, v0, off offset:4 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_store_b32 v1, v2, off offset:3716 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, v1, off offset:3716 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_large_imm_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -2613,6 +3264,19 @@ define amdgpu_kernel void @store_load_large_imm_offset_kernel() {
; GFX1030-PAL-NEXT: scratch_load_dword v0, off, s0 offset:1664 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_large_imm_offset_kernel:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 13
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 0x3000
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-PAL-NEXT: scratch_store_b32 off, v0, off offset:4 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_store_b32 v1, v2, off offset:3716 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, off offset:3716 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
bb:
%i = alloca [4096 x i32], align 4, addrspace(5)
%i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef
@@ -2658,6 +3322,21 @@ define void @store_load_large_imm_offset_foo() {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_large_imm_offset_foo:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_mov_b32_e32 v0, 13
+; GFX11-NEXT: v_mov_b32_e32 v1, 0x3000
+; GFX11-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-NEXT: scratch_store_b32 off, v0, s32 offset:4 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_store_b32 v1, v2, s32 offset:3716 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, v1, s32 offset:3716 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_large_imm_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2704,6 +3383,21 @@ define void @store_load_large_imm_offset_foo() {
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s0 offset:1664 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_large_imm_offset_foo:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 13
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 0x3000
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 15
+; GFX11-PAL-NEXT: scratch_store_b32 off, v0, s32 offset:4 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_store_b32 v1, v2, s32 offset:3716 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, s32 offset:3716 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: store_load_large_imm_offset_foo:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2762,6 +3456,18 @@ define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: store_load_vidx_sidx_offset:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_lshl_u32 v0, s0, v0, 2
+; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:1028 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v0, v0, off offset:1028 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: store_load_vidx_sidx_offset:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[4:5]
@@ -2815,6 +3521,18 @@ define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:1024 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: store_load_vidx_sidx_offset:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_load_b32 s0, s[0:1], 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-PAL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PAL-NEXT: v_add_lshl_u32 v0, s0, v0, 2
+; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:1028 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b32 v0, v0, off offset:1028 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_endpgm
; GCN-LABEL: store_load_vidx_sidx_offset:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
@@ -2861,6 +3579,18 @@ define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_i64_aligned:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: scratch_store_b64 v0, v[1:2], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b64 v[0:1], v0, off glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_i64_aligned:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2894,6 +3624,18 @@ define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) {
; GFX10-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_i64_aligned:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-PAL-NEXT: scratch_store_b64 v0, v[1:2], off dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b64 v[0:1], v0, off glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: store_load_i64_aligned:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2934,6 +3676,18 @@ define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_i64_unaligned:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: scratch_store_b64 v0, v[1:2], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b64 v[0:1], v0, off glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_i64_unaligned:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2967,6 +3721,18 @@ define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) {
; GFX10-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_i64_unaligned:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 15
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-PAL-NEXT: scratch_store_b64 v0, v[1:2], off dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b64 v[0:1], v0, off glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: store_load_i64_unaligned:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3009,6 +3775,19 @@ define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg)
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_v3i32_unaligned:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-NEXT: v_mov_b32_e32 v3, 3
+; GFX11-NEXT: scratch_store_b96 v0, v[1:3], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b96 v[0:2], v0, off glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_v3i32_unaligned:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3045,6 +3824,19 @@ define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg)
; GFX10-PAL-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_v3i32_unaligned:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, 3
+; GFX11-PAL-NEXT: scratch_store_b96 v0, v[1:3], off dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b96 v[0:2], v0, off glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: store_load_v3i32_unaligned:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3090,6 +3882,20 @@ define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg)
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_v4i32_unaligned:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-NEXT: v_mov_b32_e32 v3, 3
+; GFX11-NEXT: v_mov_b32_e32 v4, 4
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b128 v[0:3], v0, off glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_v4i32_unaligned:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3129,6 +3935,20 @@ define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg)
; GFX10-PAL-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_v4i32_unaligned:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, 2
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, 3
+; GFX11-PAL-NEXT: v_mov_b32_e32 v4, 4
+; GFX11-PAL-NEXT: scratch_store_b128 v0, v[1:4], off dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b128 v[0:3], v0, off glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: store_load_v4i32_unaligned:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3170,6 +3990,17 @@ define void @store_load_i32_negative_unaligned(i8 addrspace(5)* nocapture %arg)
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_i32_negative_unaligned:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-NEXT: scratch_store_b8 v0, v1, off offset:-1 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_u8 v0, v0, off offset:-1 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_i32_negative_unaligned:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3214,6 +4045,17 @@ define void @store_load_i32_negative_unaligned(i8 addrspace(5)* nocapture %arg)
; GFX1030-PAL-NEXT: scratch_load_ubyte v0, v0, off offset:-1 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_i32_negative_unaligned:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-PAL-NEXT: scratch_store_b8 v0, v1, off offset:-1 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_u8 v0, v0, off offset:-1 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
bb:
%ptr = getelementptr inbounds i8, i8 addrspace(5)* %arg, i32 -1
store volatile i8 1, i8 addrspace(5)* %ptr, align 1
@@ -3245,6 +4087,18 @@ define void @store_load_i32_large_negative_unaligned(i8 addrspace(5)* nocapture
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
+; GFX11-LABEL: store_load_i32_large_negative_unaligned:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-NEXT: s_movk_i32 s0, 0xef7f
+; GFX11-NEXT: scratch_store_b8 v0, v1, s0 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_u8 v0, v0, s0 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-PAL-LABEL: store_load_i32_large_negative_unaligned:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3290,6 +4144,18 @@ define void @store_load_i32_large_negative_unaligned(i8 addrspace(5)* nocapture
; GFX1030-PAL-NEXT: scratch_load_ubyte v0, v0, off offset:-129 glc dlc
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX1030-PAL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-PAL-LABEL: store_load_i32_large_negative_unaligned:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 1
+; GFX11-PAL-NEXT: s_movk_i32 s0, 0xef7f
+; GFX11-PAL-NEXT: scratch_store_b8 v0, v1, s0 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_u8 v0, v0, s0 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
bb:
%ptr = getelementptr inbounds i8, i8 addrspace(5)* %arg, i32 -4225
store volatile i8 1, i8 addrspace(5)* %ptr, align 1
@@ -3348,6 +4214,26 @@ define amdgpu_ps void @large_offset() {
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_endpgm
;
+; GFX11-LABEL: large_offset:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: v_mov_b32_e32 v1, v0
+; GFX11-NEXT: v_mov_b32_e32 v2, v0
+; GFX11-NEXT: v_mov_b32_e32 v3, v0
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], off offset:3024 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b128 v[0:3], off, off offset:3024 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, 16
+; GFX11-NEXT: v_mov_b32_e32 v1, 0x810
+; GFX11-NEXT: ;;#ASMSTART
+; GFX11-NEXT: ; use v0
+; GFX11-NEXT: ;;#ASMEND
+; GFX11-NEXT: ;;#ASMSTART
+; GFX11-NEXT: ; use v1
+; GFX11-NEXT: ;;#ASMEND
+; GFX11-NEXT: s_endpgm
+;
; GFX9-PAL-LABEL: large_offset:
; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
@@ -3427,6 +4313,26 @@ define amdgpu_ps void @large_offset() {
; GFX10-PAL-NEXT: ; use v1
; GFX10-PAL-NEXT: ;;#ASMEND
; GFX10-PAL-NEXT: s_endpgm
+;
+; GFX11-PAL-LABEL: large_offset:
+; GFX11-PAL: ; %bb.0: ; %bb
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, v0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v2, v0
+; GFX11-PAL-NEXT: v_mov_b32_e32 v3, v0
+; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], off offset:3024 dlc
+; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-PAL-NEXT: scratch_load_b128 v[0:3], off, off offset:3024 glc dlc
+; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 16
+; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 0x810
+; GFX11-PAL-NEXT: ;;#ASMSTART
+; GFX11-PAL-NEXT: ; use v0
+; GFX11-PAL-NEXT: ;;#ASMEND
+; GFX11-PAL-NEXT: ;;#ASMSTART
+; GFX11-PAL-NEXT: ; use v1
+; GFX11-PAL-NEXT: ;;#ASMEND
+; GFX11-PAL-NEXT: s_endpgm
bb:
%alloca = alloca [128 x <4 x i32>], align 16, addrspace(5)
%alloca2 = alloca [128 x <4 x i32>], align 16, addrspace(5)
More information about the llvm-commits
mailing list