[PATCH] D127576: [RISCV] Teach vsetvli insertion to handle VLEFF/VLSEGFF.
Yeting Kuo via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 13 01:03:41 PDT 2022
fakepaper56 marked 2 inline comments as done.
fakepaper56 added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:929
+
+ if (TII->isFaultFirstLoad(*DefMI)) {
+ uint64_t TSFlags = MI.getDesc().TSFlags;
----------------
craig.topper wrote:
> Please rebase now that isFaultFirstLoad isn't in RISCVInstrInfo.
Done.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1073
+ if (!DefMI ||
+ (!isVectorConfigInstr(*DefMI) && !TII->isFaultFirstLoad(*DefMI)))
return true;
----------------
craig.topper wrote:
> Can we split this if and combine it with the one below? By doing something like
>
> ```
> if (!DefMI)
> return true;
>
> if (isVectorConfigInstr(*DefMI)) {
> DefInfo = getInfoForVSETVLI(*DefMI);
> } else if (TII->isFaultFirstLoad(*DefMI)) {
> DefInfo = computeInfoForInstr(*DefMI, DefMI->getDesc().TSFlags, MRI);
> DefInfo.setAVLReg(DefMI->getOperand(1).getReg());
> } else {
> return true;
> }
> ```
>
> Along with appropriate modifications to the comments.
Done.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D127576/new/
https://reviews.llvm.org/D127576
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