[PATCH] D127576: [RISCV] Teach vsetvli insertion to handle VLEFF/VLSEGFF.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:929
+
+      if (TII->isFaultFirstLoad(*DefMI)) {
+        uint64_t TSFlags = MI.getDesc().TSFlags;
----------------
Please rebase now that isFaultFirstLoad isn't in RISCVInstrInfo.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1073
+    if (!DefMI ||
+        (!isVectorConfigInstr(*DefMI) && !TII->isFaultFirstLoad(*DefMI)))
       return true;
----------------
Can we split this if and combine it with the one below? By doing something like

```
if (!DefMI)
  return true;

if (isVectorConfigInstr(*DefMI)) {
  DefInfo = getInfoForVSETVLI(*DefMI);
} else if (TII->isFaultFirstLoad(*DefMI)) {
  DefInfo = computeInfoForInstr(*DefMI, DefMI->getDesc().TSFlags, MRI);
  DefInfo.setAVLReg(DefMI->getOperand(1).getReg());
} else {
  return true;
}
```

Along with appropriate modifications to the comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1157
 
-    // If this is something that updates VL/VTYPE that we don't know about, set
-    // the state to unknown.
-    if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
-        MI.modifiesRegister(RISCV::VTYPE)) {
+    if (TII->isFaultFirstLoad(MI)) {
+      // Change AVL to the vl-output of VLEFF/VLSEGFF.
----------------
This code is identical to the code on line 975, except for which varaible we update. Could this use a shared function?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127576/new/

https://reviews.llvm.org/D127576