[PATCH] D127604: [SLP][X86] Add 32-bit vector stores to help vectorization opportunities

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: xbolva00, ABataev, pengfei, craig.topper.
Herald added subscribers: jsji, vporpo, StephenFan, hiraditya.
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Building on the work on D124284 <https://reviews.llvm.org/D124284>, this patch tags v4i8 and v2i16 vector loads as custom, enabling SLP to try to vectorize these types ending in a partial store (using the SSE MOVD instruction) - we already do something similar for 64-bit vector types.

I haven't had time to properly test these (my last testing was with D103925 <https://reviews.llvm.org/D103925> which attempted something similar), so if anyone has a working test suite instance to hand that'd be very useful!


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127604

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/Transforms/SLPVectorizer/X86/arith-add-load.ll
  llvm/test/Transforms/SLPVectorizer/X86/arith-and-const-load.ll
  llvm/test/Transforms/SLPVectorizer/X86/arith-mul-load.ll

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