[llvm] b350ab7 - [X86] Add regression test for rGea8fb3b60196

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-06-12T15:40:36+01:00
New Revision: b350ab7437d272cca27089189be56361fa39eec5

URL: https://github.com/llvm/llvm-project/commit/b350ab7437d272cca27089189be56361fa39eec5
DIFF: https://github.com/llvm/llvm-project/commit/b350ab7437d272cca27089189be56361fa39eec5.diff

LOG: [X86] Add regression test for rGea8fb3b60196

Reduced from test case reported by @srj for the concatenation of VSELECT/BLENDV nodes

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/vselect-avx.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/vselect-avx.ll b/llvm/test/CodeGen/X86/vselect-avx.ll
index f8072ff00a135..9a58d7b587444 100644
--- a/llvm/test/CodeGen/X86/vselect-avx.ll
+++ b/llvm/test/CodeGen/X86/vselect-avx.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 
@@ -197,3 +197,23 @@ define void @blendv_split(<8 x i32>* %p, <8 x i32> %cond, <8 x i32> %a, <8 x i32
   store <8 x i32> %sel, <8 x i32>* %p, align 4
   ret void
 }
+
+define void @vselect_concat() {
+; AVX-LABEL: vselect_concat:
+; AVX:       ## %bb.0: ## %entry
+; AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
+; AVX-NEXT:    vmovaps %ymm0, (%rax)
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
+entry:
+  %0 = load <8 x i32>, <8 x i32>* undef
+  %1 = shufflevector <8 x i32> zeroinitializer, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %2 = shufflevector <8 x i32> %0, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> zeroinitializer, <4 x i32> %1, <4 x i32> %2
+  %4 = shufflevector <8 x i32> zeroinitializer, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %5 = shufflevector <8 x i32> %0, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %6 = select <4 x i1> zeroinitializer, <4 x i32> %4, <4 x i32> %5
+  %7 = shufflevector <4 x i32> %3, <4 x i32> %6, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  store <8 x i32> %7, <8 x i32>* undef
+  ret void
+}