[llvm] 82fcd73 - [AArch64] Add extra faddp codegen tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 11 04:57:53 PDT 2022
Author: David Green
Date: 2022-06-11T12:57:48+01:00
New Revision: 82fcd7397a5939a9f0148513cc7b6883a00a16b0
URL: https://github.com/llvm/llvm-project/commit/82fcd7397a5939a9f0148513cc7b6883a00a16b0
DIFF: https://github.com/llvm/llvm-project/commit/82fcd7397a5939a9f0148513cc7b6883a00a16b0.diff
LOG: [AArch64] Add extra faddp codegen tests. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/faddp-half.ll
llvm/test/CodeGen/AArch64/faddp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/faddp-half.ll b/llvm/test/CodeGen/AArch64/faddp-half.ll
index 6e3a409edce6..8413ab024600 100644
--- a/llvm/test/CodeGen/AArch64/faddp-half.ll
+++ b/llvm/test/CodeGen/AArch64/faddp-half.ll
@@ -139,3 +139,202 @@ entry:
%1 = extractelement <8 x half> %0, i32 0
ret half %1
}
+
+define <8 x half> @addp_v8f16(<8 x half> %a) {
+; CHECK-LABEL: addp_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 v1.8h, v0.8h
+; CHECK-NEXT: fadd v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+;
+; CHECKNOFP16-LABEL: addp_v8f16:
+; CHECKNOFP16: // %bb.0: // %entry
+; CHECKNOFP16-NEXT: rev32 v2.8h, v0.8h
+; CHECKNOFP16-NEXT: mov h1, v0.h[1]
+; CHECKNOFP16-NEXT: fcvt s4, h0
+; CHECKNOFP16-NEXT: mov h6, v0.h[2]
+; CHECKNOFP16-NEXT: mov h16, v0.h[3]
+; CHECKNOFP16-NEXT: mov h3, v2.h[1]
+; CHECKNOFP16-NEXT: fcvt s1, h1
+; CHECKNOFP16-NEXT: fcvt s5, h2
+; CHECKNOFP16-NEXT: mov h7, v2.h[2]
+; CHECKNOFP16-NEXT: mov h17, v2.h[3]
+; CHECKNOFP16-NEXT: fcvt s3, h3
+; CHECKNOFP16-NEXT: fadd s4, s5, s4
+; CHECKNOFP16-NEXT: fcvt s5, h6
+; CHECKNOFP16-NEXT: fcvt s6, h7
+; CHECKNOFP16-NEXT: fcvt s7, h16
+; CHECKNOFP16-NEXT: fcvt s16, h17
+; CHECKNOFP16-NEXT: fadd s3, s3, s1
+; CHECKNOFP16-NEXT: fcvt h1, s4
+; CHECKNOFP16-NEXT: fadd s4, s6, s5
+; CHECKNOFP16-NEXT: mov h5, v0.h[4]
+; CHECKNOFP16-NEXT: mov h6, v2.h[4]
+; CHECKNOFP16-NEXT: fadd s7, s16, s7
+; CHECKNOFP16-NEXT: fcvt h3, s3
+; CHECKNOFP16-NEXT: mov h16, v2.h[5]
+; CHECKNOFP16-NEXT: fcvt h7, s7
+; CHECKNOFP16-NEXT: mov v1.h[1], v3.h[0]
+; CHECKNOFP16-NEXT: fcvt h3, s4
+; CHECKNOFP16-NEXT: fcvt s4, h5
+; CHECKNOFP16-NEXT: fcvt s5, h6
+; CHECKNOFP16-NEXT: mov h6, v0.h[5]
+; CHECKNOFP16-NEXT: mov v1.h[2], v3.h[0]
+; CHECKNOFP16-NEXT: fadd s3, s5, s4
+; CHECKNOFP16-NEXT: fcvt s4, h6
+; CHECKNOFP16-NEXT: fcvt s5, h16
+; CHECKNOFP16-NEXT: mov h6, v0.h[6]
+; CHECKNOFP16-NEXT: mov h16, v2.h[6]
+; CHECKNOFP16-NEXT: mov h0, v0.h[7]
+; CHECKNOFP16-NEXT: mov v1.h[3], v7.h[0]
+; CHECKNOFP16-NEXT: mov h2, v2.h[7]
+; CHECKNOFP16-NEXT: fcvt h3, s3
+; CHECKNOFP16-NEXT: fadd s4, s5, s4
+; CHECKNOFP16-NEXT: fcvt s5, h6
+; CHECKNOFP16-NEXT: fcvt s6, h16
+; CHECKNOFP16-NEXT: fcvt s0, h0
+; CHECKNOFP16-NEXT: fcvt s2, h2
+; CHECKNOFP16-NEXT: mov v1.h[4], v3.h[0]
+; CHECKNOFP16-NEXT: fcvt h3, s4
+; CHECKNOFP16-NEXT: fadd s4, s6, s5
+; CHECKNOFP16-NEXT: fadd s0, s2, s0
+; CHECKNOFP16-NEXT: mov v1.h[5], v3.h[0]
+; CHECKNOFP16-NEXT: fcvt h3, s4
+; CHECKNOFP16-NEXT: fcvt h0, s0
+; CHECKNOFP16-NEXT: mov v1.h[6], v3.h[0]
+; CHECKNOFP16-NEXT: mov v1.h[7], v0.h[0]
+; CHECKNOFP16-NEXT: mov v0.16b, v1.16b
+; CHECKNOFP16-NEXT: ret
+entry:
+ %s = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+ %b = fadd reassoc <8 x half> %s, %a
+ ret <8 x half> %b
+}
+
+define <16 x half> @addp_v16f16(<16 x half> %a) {
+; CHECK-LABEL: addp_v16f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 v2.8h, v0.8h
+; CHECK-NEXT: rev32 v3.8h, v1.8h
+; CHECK-NEXT: fadd v0.8h, v2.8h, v0.8h
+; CHECK-NEXT: fadd v1.8h, v3.8h, v1.8h
+; CHECK-NEXT: ret
+;
+; CHECKNOFP16-LABEL: addp_v16f16:
+; CHECKNOFP16: // %bb.0: // %entry
+; CHECKNOFP16-NEXT: rev32 v5.8h, v0.8h
+; CHECKNOFP16-NEXT: mov h6, v0.h[1]
+; CHECKNOFP16-NEXT: rev32 v4.8h, v1.8h
+; CHECKNOFP16-NEXT: fcvt s2, h0
+; CHECKNOFP16-NEXT: mov h7, v0.h[2]
+; CHECKNOFP16-NEXT: mov h16, v1.h[1]
+; CHECKNOFP16-NEXT: mov h3, v5.h[1]
+; CHECKNOFP16-NEXT: fcvt s6, h6
+; CHECKNOFP16-NEXT: mov h17, v5.h[2]
+; CHECKNOFP16-NEXT: mov h18, v4.h[1]
+; CHECKNOFP16-NEXT: fcvt s19, h5
+; CHECKNOFP16-NEXT: fcvt s20, h1
+; CHECKNOFP16-NEXT: fcvt s7, h7
+; CHECKNOFP16-NEXT: fcvt s16, h16
+; CHECKNOFP16-NEXT: fcvt s3, h3
+; CHECKNOFP16-NEXT: fcvt s21, h4
+; CHECKNOFP16-NEXT: fcvt s17, h17
+; CHECKNOFP16-NEXT: fcvt s18, h18
+; CHECKNOFP16-NEXT: fadd s2, s19, s2
+; CHECKNOFP16-NEXT: mov h19, v5.h[3]
+; CHECKNOFP16-NEXT: fadd s3, s3, s6
+; CHECKNOFP16-NEXT: mov h6, v0.h[3]
+; CHECKNOFP16-NEXT: fadd s20, s21, s20
+; CHECKNOFP16-NEXT: fadd s7, s17, s7
+; CHECKNOFP16-NEXT: fadd s16, s18, s16
+; CHECKNOFP16-NEXT: fcvt h2, s2
+; CHECKNOFP16-NEXT: fcvt s18, h19
+; CHECKNOFP16-NEXT: mov h19, v0.h[5]
+; CHECKNOFP16-NEXT: fcvt h17, s3
+; CHECKNOFP16-NEXT: fcvt s6, h6
+; CHECKNOFP16-NEXT: fcvt h3, s20
+; CHECKNOFP16-NEXT: fcvt h7, s7
+; CHECKNOFP16-NEXT: fcvt h16, s16
+; CHECKNOFP16-NEXT: mov h20, v5.h[5]
+; CHECKNOFP16-NEXT: fcvt s19, h19
+; CHECKNOFP16-NEXT: mov v2.h[1], v17.h[0]
+; CHECKNOFP16-NEXT: fadd s6, s18, s6
+; CHECKNOFP16-NEXT: mov h17, v0.h[4]
+; CHECKNOFP16-NEXT: mov h18, v5.h[4]
+; CHECKNOFP16-NEXT: fcvt s20, h20
+; CHECKNOFP16-NEXT: mov v3.h[1], v16.h[0]
+; CHECKNOFP16-NEXT: mov v2.h[2], v7.h[0]
+; CHECKNOFP16-NEXT: fcvt h6, s6
+; CHECKNOFP16-NEXT: fcvt s7, h17
+; CHECKNOFP16-NEXT: fcvt s16, h18
+; CHECKNOFP16-NEXT: mov h17, v1.h[2]
+; CHECKNOFP16-NEXT: mov h18, v4.h[2]
+; CHECKNOFP16-NEXT: fadd s19, s20, s19
+; CHECKNOFP16-NEXT: mov h20, v4.h[4]
+; CHECKNOFP16-NEXT: mov v2.h[3], v6.h[0]
+; CHECKNOFP16-NEXT: fadd s6, s16, s7
+; CHECKNOFP16-NEXT: fcvt s7, h17
+; CHECKNOFP16-NEXT: fcvt s16, h18
+; CHECKNOFP16-NEXT: mov h17, v1.h[3]
+; CHECKNOFP16-NEXT: mov h18, v4.h[3]
+; CHECKNOFP16-NEXT: fcvt h6, s6
+; CHECKNOFP16-NEXT: fadd s7, s16, s7
+; CHECKNOFP16-NEXT: mov h16, v1.h[4]
+; CHECKNOFP16-NEXT: fcvt s17, h17
+; CHECKNOFP16-NEXT: fcvt s18, h18
+; CHECKNOFP16-NEXT: mov v2.h[4], v6.h[0]
+; CHECKNOFP16-NEXT: fcvt h6, s7
+; CHECKNOFP16-NEXT: fadd s7, s18, s17
+; CHECKNOFP16-NEXT: fcvt s16, h16
+; CHECKNOFP16-NEXT: fcvt s17, h20
+; CHECKNOFP16-NEXT: fcvt h18, s19
+; CHECKNOFP16-NEXT: mov v3.h[2], v6.h[0]
+; CHECKNOFP16-NEXT: fcvt h6, s7
+; CHECKNOFP16-NEXT: fadd s7, s17, s16
+; CHECKNOFP16-NEXT: mov h16, v1.h[5]
+; CHECKNOFP16-NEXT: mov h17, v4.h[5]
+; CHECKNOFP16-NEXT: mov v2.h[5], v18.h[0]
+; CHECKNOFP16-NEXT: mov h18, v5.h[6]
+; CHECKNOFP16-NEXT: mov v3.h[3], v6.h[0]
+; CHECKNOFP16-NEXT: fcvt h6, s7
+; CHECKNOFP16-NEXT: fcvt s7, h16
+; CHECKNOFP16-NEXT: fcvt s16, h17
+; CHECKNOFP16-NEXT: mov h17, v0.h[6]
+; CHECKNOFP16-NEXT: fcvt s18, h18
+; CHECKNOFP16-NEXT: mov h0, v0.h[7]
+; CHECKNOFP16-NEXT: mov h5, v5.h[7]
+; CHECKNOFP16-NEXT: mov v3.h[4], v6.h[0]
+; CHECKNOFP16-NEXT: fadd s6, s16, s7
+; CHECKNOFP16-NEXT: mov h7, v1.h[6]
+; CHECKNOFP16-NEXT: mov h16, v4.h[6]
+; CHECKNOFP16-NEXT: fcvt s17, h17
+; CHECKNOFP16-NEXT: mov h1, v1.h[7]
+; CHECKNOFP16-NEXT: mov h4, v4.h[7]
+; CHECKNOFP16-NEXT: fcvt s0, h0
+; CHECKNOFP16-NEXT: fcvt h6, s6
+; CHECKNOFP16-NEXT: fcvt s5, h5
+; CHECKNOFP16-NEXT: fcvt s7, h7
+; CHECKNOFP16-NEXT: fcvt s16, h16
+; CHECKNOFP16-NEXT: fadd s17, s18, s17
+; CHECKNOFP16-NEXT: fcvt s1, h1
+; CHECKNOFP16-NEXT: fcvt s4, h4
+; CHECKNOFP16-NEXT: mov v3.h[5], v6.h[0]
+; CHECKNOFP16-NEXT: fadd s0, s5, s0
+; CHECKNOFP16-NEXT: fadd s7, s16, s7
+; CHECKNOFP16-NEXT: fcvt h6, s17
+; CHECKNOFP16-NEXT: fadd s1, s4, s1
+; CHECKNOFP16-NEXT: fcvt h0, s0
+; CHECKNOFP16-NEXT: fcvt h4, s7
+; CHECKNOFP16-NEXT: mov v2.h[6], v6.h[0]
+; CHECKNOFP16-NEXT: fcvt h1, s1
+; CHECKNOFP16-NEXT: mov v3.h[6], v4.h[0]
+; CHECKNOFP16-NEXT: mov v2.h[7], v0.h[0]
+; CHECKNOFP16-NEXT: mov v3.h[7], v1.h[0]
+; CHECKNOFP16-NEXT: mov v0.16b, v2.16b
+; CHECKNOFP16-NEXT: mov v1.16b, v3.16b
+; CHECKNOFP16-NEXT: ret
+entry:
+ %s = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
+ %b = fadd reassoc <16 x half> %s, %a
+ ret <16 x half> %b
+}
diff --git a/llvm/test/CodeGen/AArch64/faddp.ll b/llvm/test/CodeGen/AArch64/faddp.ll
index 1476f7bcda5e..3802b2fee9c4 100644
--- a/llvm/test/CodeGen/AArch64/faddp.ll
+++ b/llvm/test/CodeGen/AArch64/faddp.ll
@@ -175,6 +175,92 @@ entry:
ret double %1
}
+
+define <2 x double> @addp_v2f64(<2 x double> %a) {
+; CHECK-LABEL: addp_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: fadd v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %s = shufflevector <2 x double> %a, <2 x double> poison, <2 x i32> <i32 1, i32 0>
+ %b = fadd reassoc <2 x double> %s, %a
+ ret <2 x double> %b
+}
+
+define <4 x double> @addp_v4f64(<4 x double> %a) {
+; CHECK-LABEL: addp_v4f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: fadd v0.2d, v2.2d, v0.2d
+; CHECK-NEXT: fadd v1.2d, v3.2d, v1.2d
+; CHECK-NEXT: ret
+entry:
+ %s = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ %b = fadd reassoc <4 x double> %s, %a
+ ret <4 x double> %b
+}
+
+define <4 x float> @addp_v4f32(<4 x float> %a) {
+; CHECK-LABEL: addp_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v1.4s, v0.4s
+; CHECK-NEXT: fadd v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %s = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ %b = fadd reassoc <4 x float> %s, %a
+ ret <4 x float> %b
+}
+
+define <8 x float> @addp_v8f32(<8 x float> %a) {
+; CHECK-LABEL: addp_v8f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v2.4s, v0.4s
+; CHECK-NEXT: rev64 v3.4s, v1.4s
+; CHECK-NEXT: fadd v0.4s, v2.4s, v0.4s
+; CHECK-NEXT: fadd v1.4s, v3.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %s = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+ %b = fadd <8 x float> %s, %a
+ ret <8 x float> %b
+}
+
+define <8 x float> @addp_v8f32_slow(<8 x float> %a) {
+; CHECK-LABEL: addp_v8f32_slow:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v2.4s, v0.4s
+; CHECK-NEXT: rev64 v3.4s, v1.4s
+; CHECK-NEXT: fadd v0.4s, v2.4s, v0.4s
+; CHECK-NEXT: fadd v1.4s, v3.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %s = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+ %b = fadd reassoc <8 x float> %s, %a
+ ret <8 x float> %b
+}
+
+define <16 x float> @addp_v16f32(<16 x float> %a) {
+; CHECK-LABEL: addp_v16f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v4.4s, v0.4s
+; CHECK-NEXT: rev64 v5.4s, v1.4s
+; CHECK-NEXT: rev64 v6.4s, v2.4s
+; CHECK-NEXT: rev64 v7.4s, v3.4s
+; CHECK-NEXT: fadd v0.4s, v4.4s, v0.4s
+; CHECK-NEXT: fadd v1.4s, v5.4s, v1.4s
+; CHECK-NEXT: fadd v2.4s, v6.4s, v2.4s
+; CHECK-NEXT: fadd v3.4s, v7.4s, v3.4s
+; CHECK-NEXT: ret
+entry:
+ %s = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
+ %b = fadd reassoc <16 x float> %s, %a
+ ret <16 x float> %b
+}
+
+
attributes #0 = { strictfp }
declare <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float>, <2 x float>, metadata, metadata)
More information about the llvm-commits
mailing list