[PATCH] D127549: RISCV: handle 64-bit PCREL data relocations

[Saleem Abdulrasool via Phabricator via llvm-commits]

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We would previously fail to handle 64-bit PC-relative relocations on
RISCV.  This was exposed by trying to build with
`-fprofile-instr-generate`.  The original changes restricted the
relocation handling to the text segment as the paired relocations to be
relaxed by the linker were undesirable in the debug and eh_frame
sections.  We now make this explicit to handle the general case for the
data relocations as well.  There is a small optimization here that is
missing: when building in the compact code model, we should relax this
pair-wise relocation to a R_RISCV_<SIZEOF_VOID_P>_PCREL type relocation.

Fixes: #55971


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127549

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
  llvm/test/MC/RISCV/instr-profile.s

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