[llvm] 9175ab7 - [AMDGPU] gfx11 SRC_POPS_EXISTING_WAVE_ID is removed

Joe Nash via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 10 10:00:38 PDT 2022


Author: Joe Nash
Date: 2022-06-10T12:32:22-04:00
New Revision: 9175ab77460807a13c56fd01488a93237514cc13

URL: https://github.com/llvm/llvm-project/commit/9175ab77460807a13c56fd01488a93237514cc13
DIFF: https://github.com/llvm/llvm-project/commit/9175ab77460807a13c56fd01488a93237514cc13.diff

LOG: [AMDGPU] gfx11 SRC_POPS_EXISTING_WAVE_ID is removed

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    llvm/test/MC/AMDGPU/gfx11_asm_operands.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index cf9eeb49d60e5..355cf5baa122c 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5625,8 +5625,9 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
   case AMDGPU::SRC_SHARED_LIMIT:
   case AMDGPU::SRC_PRIVATE_BASE:
   case AMDGPU::SRC_PRIVATE_LIMIT:
-  case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
     return isGFX9Plus();
+  case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
+    return isGFX9Plus() && !isGFX11Plus();
   case AMDGPU::TBA:
   case AMDGPU::TBA_LO:
   case AMDGPU::TBA_HI:

diff  --git a/llvm/test/MC/AMDGPU/gfx11_asm_operands.s b/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
index d77962e359420..ee2ccf1e8334c 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
@@ -105,3 +105,39 @@ v_mov_b32 v0, lds_direct
 v_mov_b32 v0, src_lds_direct
 // GFX10: encoding: [0xfe,0x02,0x00,0x7e]
 // GFX11-ERR: error: lds_direct is not supported on this GPU
+
+//---------------------------------------------------------------------------//
+// POPS_EXITING_WAVE_ID
+//---------------------------------------------------------------------------//
+
+s_add_i32 s0, src_pops_exiting_wave_id, s1
+// GFX10: encoding: [0xef,0x01,0x00,0x81]
+// GFX11-ERR: error: register not available on this GPU
+
+s_add_i32 s0, s1, src_pops_exiting_wave_id
+// GFX10: encoding: [0x01,0xef,0x00,0x81]
+// GFX11-ERR: error: register not available on this GPU
+
+s_add_i32 s0, pops_exiting_wave_id, s1
+// GFX10: encoding: [0xef,0x01,0x00,0x81]
+// GFX11-ERR: error: register not available on this GPU
+
+s_add_i32 s0, s1, pops_exiting_wave_id
+// GFX10: encoding: [0x01,0xef,0x00,0x81]
+// GFX11-ERR: error: register not available on this GPU
+
+v_add_co_u32 v0, s0, pops_exiting_wave_id, v1
+// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0xef,0x02,0x02,0x00]
+// GFX11-ERR: error: register not available on this GPU
+
+v_add_co_u32 v0, s0, src_pops_exiting_wave_id, v1
+// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0xef,0x02,0x02,0x00]
+// GFX11-ERR: error: register not available on this GPU
+
+v_add_co_u32 v0, s0, v1, pops_exiting_wave_id
+// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0x01,0xdf,0x01,0x00]
+// GFX11-ERR: error: register not available on this GPU
+
+v_add_co_u32 v0, s0, v1, src_pops_exiting_wave_id
+// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0x01,0xdf,0x01,0x00]
+// GFX11-ERR: error: register not available on this GPU


        


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