[llvm] 9311637 - Revert "[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`"

[Shao-Ce SUN via llvm-commits]

Author: Shao-Ce SUN
Date: 2022-06-11T00:03:04+08:00
New Revision: 93116374e73bac16c720d8272006b826e4280b4b

URL: https://github.com/llvm/llvm-project/commit/93116374e73bac16c720d8272006b826e4280b4b
DIFF: https://github.com/llvm/llvm-project/commit/93116374e73bac16c720d8272006b826e4280b4b.diff

LOG: Revert "[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`"

This reverts commit e018e493c1ac514504bbaa1d1396aec025142a31.

There are some problems with this commit,
related revision: https://reviews.llvm.org/D127477

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index 9b69170d1c4a..b3c53c9bd526 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -182,4 +182,9 @@ void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
     OS << ", mu";
 }
 
+bool isFaultFirstLoad(const MachineInstr &MI) {
+  return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
+         !MI.isInlineAsm();
+}
+
 } // namespace llvm

diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index c7d88d80d723..9e343a21e7bc 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -433,13 +433,7 @@ void printVType(unsigned VType, raw_ostream &OS);
 
 } // namespace RISCVVType
 
-namespace RISCVVInstInfo {
-inline static bool isFaultFirstLoad(const MachineInstr &MI) {
-  return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
-         !MI.isInlineAsm();
-}
-} // namespace RISCVVInstInfo
-
+bool isFaultFirstLoad(const MachineInstr &MI);
 } // namespace llvm
 
 #endif

diff  --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 9db14dbcc55d..866a6d8edb39 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1414,7 +1414,7 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) {
 void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
   for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
     MachineInstr &MI = *I++;
-    if (RISCVVInstInfo::isFaultFirstLoad(MI)) {
+    if (isFaultFirstLoad(MI)) {
       Register VLOutput = MI.getOperand(1).getReg();
       if (!MRI->use_nodbg_empty(VLOutput))
         BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),

diff  --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
index 530b9b03f74a..e341f82db95d 100644
--- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -158,7 +158,7 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
   if (RISCVII::hasSEWOp(TSFlags))
     --NumOps;
 
-  bool hasVLOutput = RISCVVInstInfo::isFaultFirstLoad(*MI);
+  bool hasVLOutput = isFaultFirstLoad(*MI);
   for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
     const MachineOperand &MO = MI->getOperand(OpNo);
     // Skip vl ouput. It should be the second output.