[llvm] 2b83467 - [RISCV] Broaden cost model coverage for fixed vectors w/i1 element type
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 10 08:13:26 PDT 2022
Author: Philip Reames
Date: 2022-06-10T08:12:42-07:00
New Revision: 2b83467d9ea148afdd4ea0daa43c5e0f4b35e346
URL: https://github.com/llvm/llvm-project/commit/2b83467d9ea148afdd4ea0daa43c5e0f4b35e346
DIFF: https://github.com/llvm/llvm-project/commit/2b83467d9ea148afdd4ea0daa43c5e0f4b35e346.diff
LOG: [RISCV] Broaden cost model coverage for fixed vectors w/i1 element type
Added:
Modified:
llvm/test/Analysis/CostModel/RISCV/reduce-add.ll
llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll
Removed:
################################################################################
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-add.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-add.ll
index dd4001166c138..c1eb1357138be 100644
--- a/llvm/test/Analysis/CostModel/RISCV/reduce-add.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-add.ll
@@ -2,6 +2,40 @@
; RUN: opt < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV32
; RUN: opt < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV64
+define i32 @reduce_i1(i32 %arg) {
+; RISCV32-LABEL: 'reduce_i1'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V4 = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 121 for instruction: %V8 = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 321 for instruction: %V16 = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 801 for instruction: %V32 = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1921 for instruction: %V64 = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 4481 for instruction: %V128 = call i1 @llvm.vector.reduce.add.v128i1(<128 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+; RISCV64-LABEL: 'reduce_i1'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V4 = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 121 for instruction: %V8 = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 321 for instruction: %V16 = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 801 for instruction: %V32 = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1921 for instruction: %V64 = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 4481 for instruction: %V128 = call i1 @llvm.vector.reduce.add.v128i1(<128 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+ %V1 = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> undef)
+ %V2 = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> undef)
+ %V4 = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> undef)
+ %V8 = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> undef)
+ %V16 = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> undef)
+ %V32 = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> undef)
+ %V64 = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> undef)
+ %V128 = call i1 @llvm.vector.reduce.add.v128i1(<128 x i1> undef)
+ ret i32 undef
+}
+
define i32 @reduce_i8(i32 %arg) {
; RISCV32-LABEL: 'reduce_i8'
; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> undef)
@@ -138,6 +172,14 @@ define i32 @reduce_i64(i32 %arg) {
ret i32 undef
}
+declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1>)
+declare i1 @llvm.vector.reduce.add.v2i1(<2 x i1>)
+declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1>)
+declare i1 @llvm.vector.reduce.add.v8i1(<8 x i1>)
+declare i1 @llvm.vector.reduce.add.v16i1(<16 x i1>)
+declare i1 @llvm.vector.reduce.add.v32i1(<32 x i1>)
+declare i1 @llvm.vector.reduce.add.v64i1(<64 x i1>)
+declare i1 @llvm.vector.reduce.add.v128i1(<128 x i1>)
declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-max.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
index f22452e0403a5..bcce5ff9a6cc9 100644
--- a/llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
@@ -2,6 +2,40 @@
; RUN: opt < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV32
; RUN: opt < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV64
+define i32 @reduce_umin_i1(i32 %arg) {
+; RISCV32-LABEL: 'reduce_umin_i1'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.umax.v2i1(<2 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i1 @llvm.vector.reduce.umax.v8i1(<8 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i1 @llvm.vector.reduce.umax.v16i1(<16 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i1 @llvm.vector.reduce.umax.v32i1(<32 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i1 @llvm.vector.reduce.umax.v64i1(<64 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.umax.v128i1(<128 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+; RISCV64-LABEL: 'reduce_umin_i1'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.umax.v2i1(<2 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i1 @llvm.vector.reduce.umax.v8i1(<8 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i1 @llvm.vector.reduce.umax.v16i1(<16 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i1 @llvm.vector.reduce.umax.v32i1(<32 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i1 @llvm.vector.reduce.umax.v64i1(<64 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.umax.v128i1(<128 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+ %V1 = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> undef)
+ %V2 = call i1 @llvm.vector.reduce.umax.v2i1(<2 x i1> undef)
+ %V4 = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> undef)
+ %V8 = call i1 @llvm.vector.reduce.umax.v8i1(<8 x i1> undef)
+ %V16 = call i1 @llvm.vector.reduce.umax.v16i1(<16 x i1> undef)
+ %V32 = call i1 @llvm.vector.reduce.umax.v32i1(<32 x i1> undef)
+ %V64 = call i1 @llvm.vector.reduce.umax.v64i1(<64 x i1> undef)
+ %V128 = call i1 @llvm.vector.reduce.umax.v128i1(<128 x i1> undef)
+ ret i32 undef
+}
+
define i32 @reduce_umax_i8(i32 %arg) {
; RISCV32-LABEL: 'reduce_umax_i8'
; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> undef)
@@ -138,6 +172,40 @@ define i32 @reduce_umax_i64(i32 %arg) {
ret i32 undef
}
+define i32 @reduce_smin_i1(i32 %arg) {
+; RISCV32-LABEL: 'reduce_smin_i1'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.smax.v2i1(<2 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i1 @llvm.vector.reduce.smax.v4i1(<4 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i1 @llvm.vector.reduce.smax.v8i1(<8 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i1 @llvm.vector.reduce.smax.v16i1(<16 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i1 @llvm.vector.reduce.smax.v32i1(<32 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i1 @llvm.vector.reduce.smax.v64i1(<64 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.smax.v128i1(<128 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+; RISCV64-LABEL: 'reduce_smin_i1'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.smax.v2i1(<2 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i1 @llvm.vector.reduce.smax.v4i1(<4 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i1 @llvm.vector.reduce.smax.v8i1(<8 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i1 @llvm.vector.reduce.smax.v16i1(<16 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i1 @llvm.vector.reduce.smax.v32i1(<32 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i1 @llvm.vector.reduce.smax.v64i1(<64 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.smax.v128i1(<128 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+ %V1 = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> undef)
+ %V2 = call i1 @llvm.vector.reduce.smax.v2i1(<2 x i1> undef)
+ %V4 = call i1 @llvm.vector.reduce.smax.v4i1(<4 x i1> undef)
+ %V8 = call i1 @llvm.vector.reduce.smax.v8i1(<8 x i1> undef)
+ %V16 = call i1 @llvm.vector.reduce.smax.v16i1(<16 x i1> undef)
+ %V32 = call i1 @llvm.vector.reduce.smax.v32i1(<32 x i1> undef)
+ %V64 = call i1 @llvm.vector.reduce.smax.v64i1(<64 x i1> undef)
+ %V128 = call i1 @llvm.vector.reduce.smax.v128i1(<128 x i1> undef)
+ ret i32 undef
+}
+
define i32 @reduce_smax_i8(i32 %arg) {
; RISCV32-LABEL: 'reduce_smax_i8'
; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i8 @llvm.vector.reduce.smax.v1i8(<1 x i8> undef)
@@ -274,6 +342,15 @@ define i32 @reduce_smax_i64(i32 %arg) {
ret i32 undef
}
+
+declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1>)
+declare i1 @llvm.vector.reduce.umax.v2i1(<2 x i1>)
+declare i1 @llvm.vector.reduce.umax.v4i1(<4 x i1>)
+declare i1 @llvm.vector.reduce.umax.v8i1(<8 x i1>)
+declare i1 @llvm.vector.reduce.umax.v16i1(<16 x i1>)
+declare i1 @llvm.vector.reduce.umax.v32i1(<32 x i1>)
+declare i1 @llvm.vector.reduce.umax.v64i1(<64 x i1>)
+declare i1 @llvm.vector.reduce.umax.v128i1(<128 x i1>)
declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
@@ -306,6 +383,14 @@ declare i64 @llvm.vector.reduce.umax.v16i64(<16 x i64>)
declare i64 @llvm.vector.reduce.umax.v32i64(<32 x i64>)
declare i64 @llvm.vector.reduce.umax.v64i64(<64 x i64>)
declare i64 @llvm.vector.reduce.umax.v128i64(<128 x i64>)
+declare i1 @llvm.vector.reduce.smax.v1i1(<1 x i1>)
+declare i1 @llvm.vector.reduce.smax.v2i1(<2 x i1>)
+declare i1 @llvm.vector.reduce.smax.v4i1(<4 x i1>)
+declare i1 @llvm.vector.reduce.smax.v8i1(<8 x i1>)
+declare i1 @llvm.vector.reduce.smax.v16i1(<16 x i1>)
+declare i1 @llvm.vector.reduce.smax.v32i1(<32 x i1>)
+declare i1 @llvm.vector.reduce.smax.v64i1(<64 x i1>)
+declare i1 @llvm.vector.reduce.smax.v128i1(<128 x i1>)
declare i8 @llvm.vector.reduce.smax.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.smax.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-min.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
index daf10e5255e0d..d241befe95232 100644
--- a/llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
@@ -2,6 +2,40 @@
; RUN: opt < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV32
; RUN: opt < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV64
+define i32 @reduce_umin_i1(i32 %arg) {
+; RISCV32-LABEL: 'reduce_umin_i1'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.umin.v2i1(<2 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i1 @llvm.vector.reduce.umin.v8i1(<8 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i1 @llvm.vector.reduce.umin.v16i1(<16 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i1 @llvm.vector.reduce.umin.v32i1(<32 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i1 @llvm.vector.reduce.umin.v64i1(<64 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.umin.v128i1(<128 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+; RISCV64-LABEL: 'reduce_umin_i1'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.umin.v2i1(<2 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i1 @llvm.vector.reduce.umin.v8i1(<8 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i1 @llvm.vector.reduce.umin.v16i1(<16 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i1 @llvm.vector.reduce.umin.v32i1(<32 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i1 @llvm.vector.reduce.umin.v64i1(<64 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.umin.v128i1(<128 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+ %V1 = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> undef)
+ %V2 = call i1 @llvm.vector.reduce.umin.v2i1(<2 x i1> undef)
+ %V4 = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> undef)
+ %V8 = call i1 @llvm.vector.reduce.umin.v8i1(<8 x i1> undef)
+ %V16 = call i1 @llvm.vector.reduce.umin.v16i1(<16 x i1> undef)
+ %V32 = call i1 @llvm.vector.reduce.umin.v32i1(<32 x i1> undef)
+ %V64 = call i1 @llvm.vector.reduce.umin.v64i1(<64 x i1> undef)
+ %V128 = call i1 @llvm.vector.reduce.umin.v128i1(<128 x i1> undef)
+ ret i32 undef
+}
+
define i32 @reduce_umin_i8(i32 %arg) {
; RISCV32-LABEL: 'reduce_umin_i8'
; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i8 @llvm.vector.reduce.umin.v1i8(<1 x i8> undef)
@@ -138,6 +172,40 @@ define i32 @reduce_umin_i64(i32 %arg) {
ret i32 undef
}
+define i32 @reduce_smin_i1(i32 %arg) {
+; RISCV32-LABEL: 'reduce_smin_i1'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.smin.v2i1(<2 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i1 @llvm.vector.reduce.smin.v8i1(<8 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i1 @llvm.vector.reduce.smin.v16i1(<16 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i1 @llvm.vector.reduce.smin.v32i1(<32 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.smin.v128i1(<128 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+; RISCV64-LABEL: 'reduce_smin_i1'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.smin.v2i1(<2 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i1 @llvm.vector.reduce.smin.v8i1(<8 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i1 @llvm.vector.reduce.smin.v16i1(<16 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i1 @llvm.vector.reduce.smin.v32i1(<32 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.smin.v128i1(<128 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+ %V1 = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> undef)
+ %V2 = call i1 @llvm.vector.reduce.smin.v2i1(<2 x i1> undef)
+ %V4 = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> undef)
+ %V8 = call i1 @llvm.vector.reduce.smin.v8i1(<8 x i1> undef)
+ %V16 = call i1 @llvm.vector.reduce.smin.v16i1(<16 x i1> undef)
+ %V32 = call i1 @llvm.vector.reduce.smin.v32i1(<32 x i1> undef)
+ %V64 = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> undef)
+ %V128 = call i1 @llvm.vector.reduce.smin.v128i1(<128 x i1> undef)
+ ret i32 undef
+}
+
define i32 @reduce_smin_i8(i32 %arg) {
; RISCV32-LABEL: 'reduce_smin_i8'
; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i8 @llvm.vector.reduce.smin.v1i8(<1 x i8> undef)
@@ -274,6 +342,14 @@ define i32 @reduce_smin_i64(i32 %arg) {
ret i32 undef
}
+declare i1 @llvm.vector.reduce.umin.v1i1(<1 x i1>)
+declare i1 @llvm.vector.reduce.umin.v2i1(<2 x i1>)
+declare i1 @llvm.vector.reduce.umin.v4i1(<4 x i1>)
+declare i1 @llvm.vector.reduce.umin.v8i1(<8 x i1>)
+declare i1 @llvm.vector.reduce.umin.v16i1(<16 x i1>)
+declare i1 @llvm.vector.reduce.umin.v32i1(<32 x i1>)
+declare i1 @llvm.vector.reduce.umin.v64i1(<64 x i1>)
+declare i1 @llvm.vector.reduce.umin.v128i1(<128 x i1>)
declare i8 @llvm.vector.reduce.umin.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
@@ -306,6 +382,14 @@ declare i64 @llvm.vector.reduce.umin.v16i64(<16 x i64>)
declare i64 @llvm.vector.reduce.umin.v32i64(<32 x i64>)
declare i64 @llvm.vector.reduce.umin.v64i64(<64 x i64>)
declare i64 @llvm.vector.reduce.umin.v128i64(<128 x i64>)
+declare i1 @llvm.vector.reduce.smin.v1i1(<1 x i1>)
+declare i1 @llvm.vector.reduce.smin.v2i1(<2 x i1>)
+declare i1 @llvm.vector.reduce.smin.v4i1(<4 x i1>)
+declare i1 @llvm.vector.reduce.smin.v8i1(<8 x i1>)
+declare i1 @llvm.vector.reduce.smin.v16i1(<16 x i1>)
+declare i1 @llvm.vector.reduce.smin.v32i1(<32 x i1>)
+declare i1 @llvm.vector.reduce.smin.v64i1(<64 x i1>)
+declare i1 @llvm.vector.reduce.smin.v128i1(<128 x i1>)
declare i8 @llvm.vector.reduce.smin.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll
index b20bef29fd27e..2816a99e94725 100644
--- a/llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll
@@ -2,6 +2,40 @@
; RUN: opt < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV32
; RUN: opt < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV64
+define i32 @reduce_i1(i32 %arg) {
+; RISCV32-LABEL: 'reduce_i1'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 137 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 331 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 781 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1807 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+; RISCV64-LABEL: 'reduce_i1'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 137 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 331 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 781 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1807 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
+;
+ %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
+ %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
+ %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
+ %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
+ %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
+ %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
+ %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
+ %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
+ ret i32 undef
+}
+
define i32 @reduce_i8(i32 %arg) {
; RISCV32-LABEL: 'reduce_i8'
; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i8 @llvm.vector.reduce.xor.v1i8(<1 x i8> undef)
@@ -138,6 +172,14 @@ define i32 @reduce_i64(i32 %arg) {
ret i32 undef
}
+declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
+declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
+declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
+declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
+declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>)
+declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1>)
+declare i1 @llvm.vector.reduce.xor.v64i1(<64 x i1>)
+declare i1 @llvm.vector.reduce.xor.v128i1(<128 x i1>)
declare i8 @llvm.vector.reduce.xor.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.xor.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
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