[llvm] 952e069 - [NFC] remove 'br undef' from InstCombine test cases
Nuno Lopes via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 10 07:29:07 PDT 2022
Author: Nuno Lopes
Date: 2022-06-10T15:28:57+01:00
New Revision: 952e069393808e503ce5494720a99f1f92685d76
URL: https://github.com/llvm/llvm-project/commit/952e069393808e503ce5494720a99f1f92685d76
DIFF: https://github.com/llvm/llvm-project/commit/952e069393808e503ce5494720a99f1f92685d76.diff
LOG: [NFC] remove 'br undef' from InstCombine test cases
This is UB and allows the compiler to give any result, so these tests weren't meaningful
InstCombine tests are now clean of 'br undef'
Added:
Modified:
llvm/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll
llvm/test/Transforms/InstCombine/X86/x86-amx.ll
llvm/test/Transforms/InstCombine/alias-recursion.ll
llvm/test/Transforms/InstCombine/cast-mul-select.ll
llvm/test/Transforms/InstCombine/catchswitch-phi.ll
llvm/test/Transforms/InstCombine/crash.ll
llvm/test/Transforms/InstCombine/debuginfo_add.ll
llvm/test/Transforms/InstCombine/div-shift-crash.ll
llvm/test/Transforms/InstCombine/div.ll
llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
llvm/test/Transforms/InstCombine/fmul-inseltpoison.ll
llvm/test/Transforms/InstCombine/fmul.ll
llvm/test/Transforms/InstCombine/fold-phi.ll
llvm/test/Transforms/InstCombine/icmp-dom.ll
llvm/test/Transforms/InstCombine/intptr6.ll
llvm/test/Transforms/InstCombine/load-combine-metadata-dominance.ll
llvm/test/Transforms/InstCombine/objsize.ll
llvm/test/Transforms/InstCombine/oss_fuzz_32759.ll
llvm/test/Transforms/InstCombine/pr51824.ll
llvm/test/Transforms/InstCombine/select.ll
llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-shl.ll
llvm/test/Transforms/InstCombine/shift-sra.ll
llvm/test/Transforms/InstCombine/shift.ll
llvm/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll
llvm/test/Transforms/InstCombine/simplify-libcalls.ll
llvm/test/Transforms/InstCombine/storemerge-dbg.ll
llvm/test/Transforms/InstCombine/type_pun-inseltpoison.ll
llvm/test/Transforms/InstCombine/type_pun.ll
llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
llvm/test/Transforms/InstCombine/vec_phi_extract.ll
llvm/test/Transforms/InstCombine/zext-or-icmp.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll b/llvm/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll
index 5c4d4a6340ab0..0c218c713fc23 100644
--- a/llvm/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll
+++ b/llvm/test/Transforms/InstCombine/2012-10-25-vector-of-pointers.ll
@@ -7,13 +7,13 @@ target triple = "x86_64-apple-macosx10.8.0"
%struct.hoge = type { double*, double*, double*, double** }
-define void @widget(%struct.hoge* nocapture %arg) nounwind uwtable ssp {
+define void @widget(%struct.hoge* nocapture %arg, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5) {
bb:
%tmp = getelementptr inbounds %struct.hoge, %struct.hoge* %arg, i64 0, i32 0
- br i1 undef, label %bb1, label %bb17
+ br i1 %c1, label %bb1, label %bb17
bb1: ; preds = %bb
- br i1 undef, label %bb2, label %bb3
+ br i1 %c2, label %bb2, label %bb3
bb2: ; preds = %bb1
br label %bb17
@@ -25,8 +25,8 @@ bb3: ; preds = %bb1
%tmp7 = sub <2 x i64> zeroinitializer, %tmp6
%tmp8 = ashr exact <2 x i64> %tmp7, <i64 3, i64 3>
%tmp9 = extractelement <2 x i64> %tmp8, i32 0
- %tmp10 = add nsw i64 undef, %tmp9
- br i1 undef, label %bb11, label %bb12
+ %tmp10 = add nsw i64 0, %tmp9
+ br i1 %c5, label %bb11, label %bb12
bb11: ; preds = %bb3
br label %bb13
@@ -35,10 +35,10 @@ bb12: ; preds = %bb3
br label %bb13
bb13: ; preds = %bb12, %bb11
- br i1 undef, label %bb16, label %bb14
+ br i1 %c3, label %bb16, label %bb14
bb14: ; preds = %bb13
- br i1 undef, label %bb16, label %bb15
+ br i1 %c4, label %bb16, label %bb15
bb15: ; preds = %bb14
br label %bb16
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-amx.ll b/llvm/test/Transforms/InstCombine/X86/x86-amx.ll
index 0f7bc245cd629..84b5a73a795d8 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-amx.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-amx.ll
@@ -1,18 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=instcombine -S < %s | FileCheck %s
-define linkonce_odr dso_local void @foo(<256 x i32>* %arrayidx16, <256 x i32>* %arrayidx29, <256 x i32>* %arrayidx35) local_unnamed_addr {
+define void @foo(<256 x i32>* %arrayidx16, <256 x i32>* %arrayidx29, <256 x i32>* %arrayidx35, i1 %c1, i1 %c2) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_COND9:%.*]]
; CHECK: for.cond9:
-; CHECK-NEXT: br i1 undef, label [[FOR_BODY14:%.*]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[FOR_BODY14:%.*]], label [[EXIT:%.*]]
; CHECK: for.body14:
; CHECK-NEXT: [[T5:%.*]] = load <256 x i32>, <256 x i32>* [[ARRAYIDX16:%.*]], align 64
; CHECK-NEXT: br label [[FOR_COND18:%.*]]
; CHECK: for.cond18:
; CHECK-NEXT: [[SUB_C_SROA_0_0:%.*]] = phi <256 x i32> [ [[T5]], [[FOR_BODY14]] ], [ [[T12:%.*]], [[FOR_BODY24:%.*]] ]
-; CHECK-NEXT: br i1 undef, label [[FOR_BODY24]], label [[FOR_COND_CLEANUP23:%.*]]
+; CHECK-NEXT: br i1 [[C2:%.*]], label [[FOR_BODY24]], label [[FOR_COND_CLEANUP23:%.*]]
; CHECK: for.cond.cleanup23:
; CHECK-NEXT: store <256 x i32> [[SUB_C_SROA_0_0]], <256 x i32>* [[ARRAYIDX16]], align 64
; CHECK-NEXT: br label [[FOR_COND9]]
@@ -31,7 +31,7 @@ define linkonce_odr dso_local void @foo(<256 x i32>* %arrayidx16, <256 x i32>* %
entry:
br label %for.cond9
for.cond9: ; preds = %for.cond, %for.cond.cleanup23
- br i1 undef, label %for.body14, label %exit
+ br i1 %c1, label %for.body14, label %exit
for.body14:
%t5 = load <256 x i32>, <256 x i32>* %arrayidx16, align 64
@@ -39,7 +39,7 @@ for.body14:
for.cond18: ; preds = %for.body24, %for.body14
%sub_c.sroa.0.0 = phi <256 x i32> [ %t5, %for.body14 ], [ %t12, %for.body24 ]
- br i1 undef, label %for.body24, label %for.cond.cleanup23
+ br i1 %c2, label %for.body24, label %for.cond.cleanup23
for.cond.cleanup23: ; preds = %for.cond18
store <256 x i32> %sub_c.sroa.0.0, <256 x i32>* %arrayidx16, align 64
diff --git a/llvm/test/Transforms/InstCombine/alias-recursion.ll b/llvm/test/Transforms/InstCombine/alias-recursion.ll
index a7e7f4e329cdc..a99bdb58837f7 100644
--- a/llvm/test/Transforms/InstCombine/alias-recursion.ll
+++ b/llvm/test/Transforms/InstCombine/alias-recursion.ll
@@ -9,13 +9,13 @@ target triple = "x86_64-pc-windows-msvc"
@vtbl = alias i8*, getelementptr inbounds ([1 x i8*], [1 x i8*]* @0, i32 0, i32 0)
-define i32 (%class.A*)* @test() {
+define i32 (%class.A*)* @test(i1 %c1, i1 %c2) {
; CHECK-LABEL: test
entry:
- br i1 undef, label %for.body, label %for.end
+ br i1 %c1, label %for.body, label %for.end
for.body: ; preds = %for.body, %entry
- br i1 undef, label %for.body, label %for.end
+ br i1 %c2, label %for.body, label %for.end
for.end: ; preds = %for.body, %entry
%A = phi i32 (%class.A*)** [ bitcast (i8** @vtbl to i32 (%class.A*)**), %for.body ], [ null, %entry ]
diff --git a/llvm/test/Transforms/InstCombine/cast-mul-select.ll b/llvm/test/Transforms/InstCombine/cast-mul-select.ll
index e68f3830b5a9d..865bbef2b9ece 100644
--- a/llvm/test/Transforms/InstCombine/cast-mul-select.ll
+++ b/llvm/test/Transforms/InstCombine/cast-mul-select.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; RUN: opt -debugify -instcombine -S < %s | FileCheck %s -check-prefix DBGINFO
@@ -111,28 +112,28 @@ define i32 @eval_sext_multi_use_in_one_inst(i32 %x) {
; If we have a transform to shrink the above 3 cases, make sure it's not
; also trying to look through multiple uses in this test and crashing.
-define void @PR36225(i32 %a, i32 %b) {
+define void @PR36225(i32 %a, i32 %b, i1 %c1, i3 %v1, i3 %v2) {
; CHECK-LABEL: @PR36225(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
; CHECK: while.body:
-; CHECK-NEXT: br i1 undef, label [[FOR_BODY3_US:%.*]], label [[FOR_BODY3:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[FOR_BODY3_US:%.*]], label [[FOR_BODY3:%.*]]
; CHECK: for.body3.us:
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[B:%.*]], 0
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i8 0, i8 4
-; CHECK-NEXT: switch i3 undef, label [[EXIT:%.*]] [
+; CHECK-NEXT: switch i3 [[V1:%.*]], label [[EXIT:%.*]] [
; CHECK-NEXT: i3 0, label [[FOR_END:%.*]]
; CHECK-NEXT: i3 -1, label [[FOR_END]]
; CHECK-NEXT: ]
; CHECK: for.body3:
-; CHECK-NEXT: switch i3 undef, label [[EXIT]] [
+; CHECK-NEXT: switch i3 [[V2:%.*]], label [[EXIT]] [
; CHECK-NEXT: i3 0, label [[FOR_END]]
; CHECK-NEXT: i3 -1, label [[FOR_END]]
; CHECK-NEXT: ]
; CHECK: for.end:
; CHECK-NEXT: [[H:%.*]] = phi i8 [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ 0, [[FOR_BODY3]] ], [ 0, [[FOR_BODY3]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[H]] to i32
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[A:%.*]]
+; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[H]] to i32
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[A:%.*]]
; CHECK-NEXT: br i1 [[CMP]], label [[EXIT]], label [[EXIT2:%.*]]
; CHECK: exit2:
; CHECK-NEXT: unreachable
@@ -144,17 +145,17 @@ entry:
while.body:
%tobool = icmp eq i32 %b, 0
- br i1 undef, label %for.body3.us, label %for.body3
+ br i1 %c1, label %for.body3.us, label %for.body3
for.body3.us:
%spec.select = select i1 %tobool, i8 0, i8 4
- switch i3 undef, label %exit [
+ switch i3 %v1, label %exit [
i3 0, label %for.end
i3 -1, label %for.end
]
for.body3:
- switch i3 undef, label %exit [
+ switch i3 %v2, label %exit [
i3 0, label %for.end
i3 -1, label %for.end
]
@@ -174,10 +175,14 @@ exit:
; Check that we don't drop debug info when a zext is removed.
define i1 @foo(i1 zeroext %b) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: ret i1 [[B:%.*]]
+;
; DBGINFO-LABEL: @foo(
-; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i1 %b, {{.*}} !DIExpression(DW_OP_LLVM_convert, 1, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value))
-; DBGINFO-NEXT: ret i1 %b
+; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i1 [[B:%.*]], metadata [[META108:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 1, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG109:![0-9]+]]
+; DBGINFO-NEXT: ret i1 [[B]], !dbg [[DBG110:![0-9]+]]
+;
- %frombool = zext i1 %b to i8
+ %frombool = zext i1 %b to i8
ret i1 %b
}
diff --git a/llvm/test/Transforms/InstCombine/catchswitch-phi.ll b/llvm/test/Transforms/InstCombine/catchswitch-phi.ll
index 9ab66235ce950..df5d3e00ab4b2 100644
--- a/llvm/test/Transforms/InstCombine/catchswitch-phi.ll
+++ b/llvm/test/Transforms/InstCombine/catchswitch-phi.ll
@@ -10,10 +10,10 @@ declare void @foo()
declare void @bar(%struct.quux*)
declare i32 @__gxx_wasm_personality_v0(...)
-define void @test() personality i8* bitcast (i32 (...)* @__gxx_wasm_personality_v0 to i8*) {
+define void @test(i1 %c1) personality i8* bitcast (i32 (...)* @__gxx_wasm_personality_v0 to i8*) {
bb:
%tmp0 = alloca %struct.blam, align 4
- br i1 undef, label %bb1, label %bb2
+ br i1 %c1, label %bb1, label %bb2
bb1: ; preds = %bb
%tmp1 = getelementptr inbounds %struct.blam, %struct.blam* %tmp0, i32 0, i32 0
diff --git a/llvm/test/Transforms/InstCombine/crash.ll b/llvm/test/Transforms/InstCombine/crash.ll
index 3ab2a99eb710e..ce25414ac98c2 100644
--- a/llvm/test/Transforms/InstCombine/crash.ll
+++ b/llvm/test/Transforms/InstCombine/crash.ll
@@ -17,10 +17,10 @@ entry:
define <2 x i64> @test1(<2 x i64> %x, <2 x i64> %y) nounwind {
entry:
%conv.i94 = bitcast <2 x i64> %y to <4 x i32> ; <<4 x i32>> [#uses=1]
- %sub.i97 = sub <4 x i32> %conv.i94, undef ; <<4 x i32>> [#uses=1]
+ %sub.i97 = sub <4 x i32> %conv.i94, poison ; <<4 x i32>> [#uses=1]
%conv3.i98 = bitcast <4 x i32> %sub.i97 to <2 x i64> ; <<2 x i64>> [#uses=2]
%conv2.i86 = bitcast <2 x i64> %conv3.i98 to <4 x i32> ; <<4 x i32>> [#uses=1]
- %cmp.i87 = icmp sgt <4 x i32> undef, %conv2.i86 ; <<4 x i1>> [#uses=1]
+ %cmp.i87 = icmp sgt <4 x i32> poison, %conv2.i86 ; <<4 x i1>> [#uses=1]
%sext.i88 = sext <4 x i1> %cmp.i87 to <4 x i32> ; <<4 x i32>> [#uses=1]
%conv3.i89 = bitcast <4 x i32> %sext.i88 to <2 x i64> ; <<2 x i64>> [#uses=1]
%and.i = and <2 x i64> %conv3.i89, %conv3.i98 ; <<2 x i64>> [#uses=1]
@@ -35,12 +35,12 @@ entry:
; PR4908
define void @test2(<1 x i16>* nocapture %b, i32* nocapture %c) nounwind ssp {
entry:
- %arrayidx = getelementptr inbounds <1 x i16>, <1 x i16>* %b, i64 undef ; <<1 x i16>*>
+ %arrayidx = getelementptr inbounds <1 x i16>, <1 x i16>* %b, i64 0 ; <<1 x i16>*>
%tmp2 = load <1 x i16>, <1 x i16>* %arrayidx ; <<1 x i16>> [#uses=1]
%tmp6 = bitcast <1 x i16> %tmp2 to i16 ; <i16> [#uses=1]
%tmp7 = zext i16 %tmp6 to i32 ; <i32> [#uses=1]
%ins = or i32 0, %tmp7 ; <i32> [#uses=1]
- %arrayidx20 = getelementptr inbounds i32, i32* %c, i64 undef ; <i32*> [#uses=1]
+ %arrayidx20 = getelementptr inbounds i32, i32* %c, i64 0 ; <i32*> [#uses=1]
store i32 %ins, i32* %arrayidx20
ret void
}
@@ -131,8 +131,8 @@ define i32 @test5a() {
ret i32 0
}
-define void @test5() personality i32 (...)* @__gxx_personality_v0 {
- store i1 true, i1* undef
+define void @test5(i1* %ptr) personality i32 (...)* @__gxx_personality_v0 {
+ store i1 true, i1* %ptr
%r = invoke i32 @test5a() to label %exit unwind label %unwind
unwind:
%exn = landingpad {i8*, i32}
@@ -207,10 +207,10 @@ declare void @_Unwind_Resume_or_Rethrow(i8*)
; rdar://7590304
-define i8* @test10(i8* %self, i8* %tmp3) personality i32 (...)* @__gxx_personality_v0 {
+define i8* @test10(i8* %self, i8* %tmp3, i1* %ptr1, i1* %ptr2) personality i32 (...)* @__gxx_personality_v0 {
entry:
- store i1 true, i1* undef
- store i1 true, i1* undef
+ store i1 true, i1* %ptr1
+ store i1 true, i1* %ptr2
invoke void @test10a()
to label %invoke.cont unwind label %try.handler ; <i8*> [#uses=0]
@@ -249,21 +249,21 @@ entry:
%cmp3 = icmp ne i32 %tmp2, 0 ; <i1> [#uses=1]
%conv4 = zext i1 %cmp3 to i32 ; <i32> [#uses=1]
%or = or i32 %conv, %conv4 ; <i32> [#uses=1]
- %cmp5 = icmp ugt i32 undef, %or ; <i1> [#uses=1]
+ %cmp5 = icmp ugt i32 0, %or ; <i1> [#uses=1]
%conv6 = zext i1 %cmp5 to i32 ; <i32> [#uses=0]
ret void
}
%s1 = type { %s2, %s2, [6 x %s2], i32, i32, i32, [1 x i32], [0 x i8] }
%s2 = type { i64 }
-define void @test13() nounwind ssp {
+define void @test13(i32* %ptr1, i32* %ptr2, i32* %ptr3) nounwind {
entry:
%0 = getelementptr inbounds %s1, %s1* null, i64 0, i32 2, i64 0, i32 0
%1 = bitcast i64* %0 to i32*
%2 = getelementptr inbounds %s1, %s1* null, i64 0, i32 2, i64 1, i32 0
%.pre = load i32, i32* %1, align 8
%3 = lshr i32 %.pre, 19
- %brmerge = or i1 undef, undef
+ %brmerge = or i1 1, 0
%4 = and i32 %3, 3
%5 = add nsw i32 %4, 1
%6 = shl i32 %5, 19
@@ -277,13 +277,13 @@ entry:
%13 = and i32 %12, -24577
%14 = or i32 %13, 16384
%15 = or i32 %14, 98304
- store i32 %15, i32* undef, align 8
+ store i32 %15, i32* %ptr1, align 8
%16 = and i32 %15, -1572865
%17 = or i32 %16, %8
- store i32 %17, i32* undef, align 8
+ store i32 %17, i32* %ptr2, align 8
%18 = and i32 %17, -449
%19 = or i32 %18, 64
- store i32 %19, i32* undef, align 8
+ store i32 %19, i32* %ptr3, align 8
unreachable
}
@@ -291,10 +291,10 @@ entry:
; PR8807
declare i32 @test14f(i8* (i8*)*) nounwind
-define void @test14() nounwind readnone {
+define void @test14(i32* %ptr) nounwind readnone {
entry:
%tmp = bitcast i32 (i8* (i8*)*)* @test14f to i32 (i32*)*
- %call10 = call i32 %tmp(i32* byval(i32) undef)
+ %call10 = call i32 %tmp(i32* byval(i32) %ptr)
ret void
}
@@ -302,7 +302,7 @@ entry:
; PR8896
@g_54 = external global [7 x i16]
-define void @test15(i32* %p_92) nounwind {
+define void @test15(i32* %p_92, i1 %c1) nounwind {
entry:
%0 = load i32, i32* %p_92, align 4
%1 = icmp ne i32 %0, 0
@@ -311,7 +311,7 @@ entry:
%4 = trunc i32 %3 to i16
%5 = sext i16 %4 to i32
%6 = trunc i32 %5 to i16
-br i1 undef, label %"3", label %"5"
+br i1 %c1, label %"3", label %"5"
"3": ; preds = %entry
%7 = sext i16 %6 to i32
@@ -349,7 +349,7 @@ define double @test16(i32 %a) nounwind {
define %struct.basic_ios *@test17() ssp {
entry:
- %add.ptr.i = getelementptr i8, i8* null, i64 undef
+ %add.ptr.i = getelementptr i8, i8* null, i64 0
%0 = bitcast i8* %add.ptr.i to %struct.basic_ios*
ret %struct.basic_ios* %0
}
diff --git a/llvm/test/Transforms/InstCombine/debuginfo_add.ll b/llvm/test/Transforms/InstCombine/debuginfo_add.ll
index fa21c19bb6a0a..e5d568becd86d 100644
--- a/llvm/test/Transforms/InstCombine/debuginfo_add.ll
+++ b/llvm/test/Transforms/InstCombine/debuginfo_add.ll
@@ -20,7 +20,7 @@ target triple = "thumbv7s-apple-ios5.0.0"
%struct.vm_object = type { i64 }
; Function Attrs: nounwind ssp
-define void @f(%struct.vm_object* %object, i64* nocapture readonly %start) local_unnamed_addr #0 !dbg !11 {
+define void @f(%struct.vm_object* %object, i64* nocapture readonly %start, i1 %c1) local_unnamed_addr #0 !dbg !11 {
entry:
tail call void @llvm.dbg.value(metadata %struct.vm_object* %object, metadata !21, metadata !DIExpression()), !dbg !27
tail call void @llvm.dbg.value(metadata i64* %start, metadata !22, metadata !DIExpression()), !dbg !28
@@ -29,7 +29,7 @@ entry:
%offset.08 = add i64 %0, -4096
tail call void @llvm.dbg.value(metadata i64 %offset.08, metadata !26, metadata !DIExpression()), !dbg !31
tail call void @llvm.dbg.value(metadata i32 undef, metadata !23, metadata !DIExpression()), !dbg !32
- br i1 undef, label %for.end, label %for.body.lr.ph, !dbg !32
+ br i1 %c1, label %for.end, label %for.body.lr.ph, !dbg !32
for.body.lr.ph: ; preds = %entry
; The 'load' and the 'add' are sunken to this basic block. So let's verify that the related dbg.values are sunken as well.
@@ -37,13 +37,13 @@ for.body.lr.ph: ; preds = %entry
; CHECK-LABEL: for.body.lr.ph:
; CHECK-NEXT: %0 = load
; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 %0, metadata !25, metadata !DIExpression()), !dbg !
- ; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 %0, metadata !26, metadata !DIExpression(DW_OP_constu, 4096, DW_OP_minus, DW_OP_stack_value)), !dbg !
+ ; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 %0, metadata !26, metadata !DIExpression(DW_OP_constu, 4096, DW_OP_minus, DW_OP_stack_value)), !dbg !
br label %for.body, !dbg !32
for.body: ; preds = %for.body.lr.ph, %for.body
; CHECK-LABEL: for.body:
%offset.010 = phi i64 [ %offset.08, %for.body.lr.ph ], [ %offset.0, %for.body ]
- %head_size.09 = phi i32 [ undef, %for.body.lr.ph ], [ %sub2, %for.body ]
+ %head_size.09 = phi i32 [ poison, %for.body.lr.ph ], [ %sub2, %for.body ]
tail call void @llvm.dbg.value(metadata i32 %head_size.09, metadata !23, metadata !DIExpression()), !dbg !31
%call = tail call i32 bitcast (i32 (...)* @use to i32 (i64, %struct.vm_object*)*)(i64 %offset.010, %struct.vm_object* %object) #3, !dbg !34
%sub2 = add i32 %head_size.09, -4096, !dbg !37
diff --git a/llvm/test/Transforms/InstCombine/div-shift-crash.ll b/llvm/test/Transforms/InstCombine/div-shift-crash.ll
index a8bee82006223..543161ef0f295 100644
--- a/llvm/test/Transforms/InstCombine/div-shift-crash.ll
+++ b/llvm/test/Transforms/InstCombine/div-shift-crash.ll
@@ -4,11 +4,10 @@ target triple = "powerpc64-unknown-linux-gnu"
%struct.S0.0.1.2.3.4.13.22.31.44.48.53.54.55.56.58.59.60.66.68.70.74.77.106.107.108.109.110.113.117.118.128.129 = type <{ i64 }>
-; Function Attrs: nounwind
-define void @main() #0 {
+define void @main(i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10) {
entry:
%l_819.i.i = alloca %struct.S0.0.1.2.3.4.13.22.31.44.48.53.54.55.56.58.59.60.66.68.70.74.77.106.107.108.109.110.113.117.118.128.129, align 8
- br i1 undef, label %land.lhs.true, label %for.cond.i
+ br i1 %c1, label %land.lhs.true, label %for.cond.i
land.lhs.true: ; preds = %entry
br label %for.cond.i
@@ -18,13 +17,13 @@ for.cond.i: ; preds = %land.lhs.true, %ent
br label %for.cond.i6.i.i
for.cond.i6.i.i: ; preds = %for.body.i8.i.i, %for.cond.i
- br i1 undef, label %for.body.i8.i.i, label %lbl_707.i.i.i
+ br i1 %c2, label %for.body.i8.i.i, label %lbl_707.i.i.i
for.body.i8.i.i: ; preds = %for.cond.i6.i.i
br label %for.cond.i6.i.i
lbl_707.i.i.i: ; preds = %for.cond.i6.i.i
- br i1 undef, label %lor.rhs.i.i.i, label %lor.end.i.i.i
+ br i1 %c3, label %lor.rhs.i.i.i, label %lor.end.i.i.i
lor.rhs.i.i.i: ; preds = %lbl_707.i.i.i
br label %lor.end.i.i.i
@@ -33,7 +32,7 @@ lor.end.i.i.i: ; preds = %lor.rhs.i.i.i, %lbl
br label %for.cond1.i.i.i.i
for.cond1.i.i.i.i: ; preds = %for.body4.i.i.i.i, %lor.end.i.i.i
- br i1 undef, label %for.body4.i.i.i.i, label %func_39.exit.i.i
+ br i1 %c4, label %for.body4.i.i.i.i, label %func_39.exit.i.i
for.body4.i.i.i.i: ; preds = %for.cond1.i.i.i.i
br label %for.cond1.i.i.i.i
@@ -43,14 +42,14 @@ func_39.exit.i.i: ; preds = %for.cond1.i.i.i.i
br label %for.cond1.i.i.i
for.cond1.i.i.i: ; preds = %safe_div_func_uint32_t_u_u.exit.i.i.i, %func_39.exit.i.i
- br i1 undef, label %for.cond7.i.i.i, label %func_11.exit.i
+ br i1 %c5, label %for.cond7.i.i.i, label %func_11.exit.i
for.cond7.i.i.i: ; preds = %for.end30.i.i.i, %for.cond1.i.i.i
%storemerge.i.i.i = phi i32 [ %sub.i.i.i, %for.end30.i.i.i ], [ 4, %for.cond1.i.i.i ]
- br i1 undef, label %for.cond22.i.i.i, label %for.end32.i.i.i
+ br i1 %c6, label %for.cond22.i.i.i, label %for.end32.i.i.i
for.cond22.i.i.i: ; preds = %for.body25.i.i.i, %for.cond7.i.i.i
- br i1 undef, label %for.body25.i.i.i, label %for.end30.i.i.i
+ br i1 %c7, label %for.body25.i.i.i, label %for.end30.i.i.i
for.body25.i.i.i: ; preds = %for.cond22.i.i.i
br label %for.cond22.i.i.i
@@ -68,7 +67,7 @@ for.end32.i.i.i: ; preds = %for.cond7.i.i.i
%cmp.i.i.i.i = icmp slt i32 %and4.i.i.i.i, 0
%sub5.i.i.i.i = sub nsw i32 -701565022, %storemerge.i.i.i
%.sub5.i.i.i.i = select i1 %cmp.i.i.i.i, i32 -701565022, i32 %sub5.i.i.i.i
- br i1 undef, label %safe_div_func_uint32_t_u_u.exit.i.i.i, label %cond.false.i.i.i.i
+ br i1 %c8, label %safe_div_func_uint32_t_u_u.exit.i.i.i, label %cond.false.i.i.i.i
cond.false.i.i.i.i: ; preds = %for.end32.i.i.i
%div.i.i.i.i = udiv i32 %conv33.i.i.i, %.sub5.i.i.i.i
@@ -80,7 +79,7 @@ safe_div_func_uint32_t_u_u.exit.i.i.i: ; preds = %cond.false.i.i.i.i,
br label %for.cond1.i.i.i
func_11.exit.i: ; preds = %for.cond1.i.i.i
- br i1 undef, label %for.body, label %for.end
+ br i1 %c9, label %for.body, label %for.end
for.body: ; preds = %func_11.exit.i
unreachable
@@ -89,7 +88,7 @@ for.end: ; preds = %func_11.exit.i
br label %for.cond15
for.cond15: ; preds = %for.cond19, %for.end
- br i1 undef, label %for.cond19, label %for.end45
+ br i1 %c10, label %for.cond19, label %for.end45
for.cond19: ; preds = %for.cond15
br label %for.cond15
@@ -97,5 +96,3 @@ for.cond19: ; preds = %for.cond15
for.end45: ; preds = %for.cond15
unreachable
}
-
-attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/Transforms/InstCombine/div.ll b/llvm/test/Transforms/InstCombine/div.ll
index bfb83956b4e4f..39864aca44cf8 100644
--- a/llvm/test/Transforms/InstCombine/div.ll
+++ b/llvm/test/Transforms/InstCombine/div.ll
@@ -38,11 +38,11 @@ define <2 x i64> @sdiv_by_minus1_vec(<2 x i64> %x) {
ret <2 x i64> %div
}
-define <2 x i64> @sdiv_by_minus1_vec_undef_elt(<2 x i64> %x) {
-; CHECK-LABEL: @sdiv_by_minus1_vec_undef_elt(
+define <2 x i64> @sdiv_by_minus1_vec_poison_elt(<2 x i64> %x) {
+; CHECK-LABEL: @sdiv_by_minus1_vec_poison_elt(
; CHECK-NEXT: ret <2 x i64> poison
;
- %div = sdiv <2 x i64> %x, <i64 -1, i64 undef>
+ %div = sdiv <2 x i64> %x, <i64 -1, i64 poison>
ret <2 x i64> %div
}
@@ -514,12 +514,12 @@ define <2 x i8> @sdiv_negated_dividend_constant_divisor_vec_splat_smin(<2 x i8>
ret <2 x i8> %d
}
-define <2 x i8> @sdiv_negated_dividend_constant_divisor_vec_undef(<2 x i8> %x) {
-; CHECK-LABEL: @sdiv_negated_dividend_constant_divisor_vec_undef(
+define <2 x i8> @sdiv_negated_dividend_constant_divisor_vec_poison(<2 x i8> %x) {
+; CHECK-LABEL: @sdiv_negated_dividend_constant_divisor_vec_poison(
; CHECK-NEXT: ret <2 x i8> poison
;
%neg = sub nsw <2 x i8> zeroinitializer, %x
- %d = sdiv <2 x i8> %neg, <i8 -128, i8 undef>
+ %d = sdiv <2 x i8> %neg, <i8 -128, i8 poison>
ret <2 x i8> %d
}
@@ -602,11 +602,11 @@ define <2 x i32> @test36vec(<2 x i32> %A) {
ret <2 x i32> %mul
}
-define i32 @test37(i32* %b) {
+define i32 @test37(i32* %b, i1 %c1) {
; CHECK-LABEL: @test37(
; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 0, i32* [[B:%.*]], align 4
-; CHECK-NEXT: br i1 undef, label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
; CHECK: lor.rhs:
; CHECK-NEXT: br label [[LOR_END]]
; CHECK: lor.end:
@@ -615,10 +615,10 @@ define i32 @test37(i32* %b) {
entry:
store i32 0, i32* %b, align 4
%0 = load i32, i32* %b, align 4
- br i1 undef, label %lor.rhs, label %lor.end
+ br i1 %c1, label %lor.rhs, label %lor.end
lor.rhs: ; preds = %entry
- %mul = mul nsw i32 undef, %0
+ %mul = mul nsw i32 1, %0
br label %lor.end
lor.end: ; preds = %lor.rhs, %entry
@@ -883,13 +883,13 @@ define <2 x i8> @negate_sdiv_vec_splat(<2 x i8> %x) {
ret <2 x i8> %neg
}
-; Dividing by undef is UB.
+; Dividing by poison is UB.
-define <2 x i8> @negate_sdiv_vec_undef_elt(<2 x i8> %x) {
-; CHECK-LABEL: @negate_sdiv_vec_undef_elt(
+define <2 x i8> @negate_sdiv_vec_poison_elt(<2 x i8> %x) {
+; CHECK-LABEL: @negate_sdiv_vec_poison_elt(
; CHECK-NEXT: ret <2 x i8> poison
;
- %div = sdiv <2 x i8> %x, <i8 undef, i8 42>
+ %div = sdiv <2 x i8> %x, <i8 poison, i8 42>
%neg = sub <2 x i8> zeroinitializer, %div
ret <2 x i8> %neg
}
@@ -1042,11 +1042,11 @@ define <2 x i8> @sdiv_by_int_min_vec_splat(<2 x i8> %x) {
ret <2 x i8> %d
}
-define <2 x i8> @sdiv_by_int_min_vec_splat_undef(<2 x i8> %x) {
-; CHECK-LABEL: @sdiv_by_int_min_vec_splat_undef(
+define <2 x i8> @sdiv_by_int_min_vec_splat_poison(<2 x i8> %x) {
+; CHECK-LABEL: @sdiv_by_int_min_vec_splat_poison(
; CHECK-NEXT: ret <2 x i8> poison
;
- %d = sdiv <2 x i8> %x, <i8 -128, i8 undef>
+ %d = sdiv <2 x i8> %x, <i8 -128, i8 poison>
ret <2 x i8> %d
}
@@ -1065,7 +1065,7 @@ define <vscale x 2 x i8> @sdiv_by_negconst_nxv2i8(<vscale x 2 x i8> %x) {
; CHECK-NEXT: [[DIV_NEG:%.*]] = sdiv <vscale x 2 x i8> [[X:%.*]], shufflevector (<vscale x 2 x i8> insertelement (<vscale x 2 x i8> poison, i8 108, i32 0), <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: ret <vscale x 2 x i8> [[DIV_NEG]]
;
- %div = sdiv <vscale x 2 x i8> %x, shufflevector (<vscale x 2 x i8> insertelement (<vscale x 2 x i8> undef, i8 -108, i32 0), <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer)
+ %div = sdiv <vscale x 2 x i8> %x, shufflevector (<vscale x 2 x i8> insertelement (<vscale x 2 x i8> poison, i8 -108, i32 0), <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer)
%sub = sub <vscale x 2 x i8> zeroinitializer, %div
ret <vscale x 2 x i8> %sub
}
@@ -1083,11 +1083,11 @@ define <2 x i8> @sdiv_by_minSigned_v2i8(<2 x i8> %x) {
define <vscale x 2 x i8> @sdiv_by_minSigned_nxv2i8(<vscale x 2 x i8> %x) {
; CHECK-LABEL: @sdiv_by_minSigned_nxv2i8(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <vscale x 2 x i8> [[X:%.*]], shufflevector (<vscale x 2 x i8> insertelement (<vscale x 2 x i8> undef, i8 -128, i32 0), <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer)
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <vscale x 2 x i8> [[X:%.*]], shufflevector (<vscale x 2 x i8> insertelement (<vscale x 2 x i8> poison, i8 -128, i32 0), <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: [[DIV_NEG:%.*]] = sext <vscale x 2 x i1> [[TMP1]] to <vscale x 2 x i8>
; CHECK-NEXT: ret <vscale x 2 x i8> [[DIV_NEG]]
;
- %div = sdiv <vscale x 2 x i8> %x, shufflevector (<vscale x 2 x i8> insertelement (<vscale x 2 x i8> undef, i8 -128, i32 0), <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer)
+ %div = sdiv <vscale x 2 x i8> %x, shufflevector (<vscale x 2 x i8> insertelement (<vscale x 2 x i8> poison, i8 -128, i32 0), <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer)
%sub = sub <vscale x 2 x i8> zeroinitializer, %div
ret <vscale x 2 x i8> %sub
}
diff --git a/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll b/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
index a7822c9eb6f35..183e22e037d2c 100644
--- a/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
+++ b/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
@@ -415,14 +415,19 @@ define void @test_memcpy_loadstore_16(i8* %dest, i8* %src) {
ret void
}
-define void @test_undefined(i8* %dest, i8* %src) {
+define void @test_undefined(i8* %dest, i8* %src, i1 %c1) {
; CHECK-LABEL: @test_undefined(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[OK:%.*]], label [[UNDEFINED:%.*]]
+; CHECK: undefined:
+; CHECK-NEXT: store i1 true, i1* undef, align 1
+; CHECK-NEXT: br label [[OK]]
+; CHECK: ok:
+; CHECK-NEXT: ret void
+;
entry:
- br i1 undef, label %ok, label %undefined
+ br i1 %c1, label %ok, label %undefined
undefined:
-; CHECK: undefined:
-; CHECK-NEXT: store i1 true, i1* undef
-; CHECK-NEXT: br label %ok
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %dest, i8* align 16 %src, i32 7, i32 4)
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %dest, i8* align 16 %src, i32 -8, i32 4)
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %dest, i8* align 16 %src, i32 7, i32 4)
diff --git a/llvm/test/Transforms/InstCombine/fmul-inseltpoison.ll b/llvm/test/Transforms/InstCombine/fmul-inseltpoison.ll
index c35c228d79cd1..d0dea471e4960 100644
--- a/llvm/test/Transforms/InstCombine/fmul-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/fmul-inseltpoison.ll
@@ -5,13 +5,13 @@
; poison
; Don't crash when attempting to cast a constant FMul to an instruction.
-define void @test8(i32* %inout) {
+define void @test8(i32* %inout, i1 %c1) {
; CHECK-LABEL: @test8(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: [[LOCAL_VAR_7_0:%.*]] = phi <4 x float> [ <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, [[ENTRY:%.*]] ], [ [[TMP0:%.*]], [[FOR_BODY:%.*]] ]
-; CHECK-NEXT: br i1 undef, label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[FOR_BODY]], label [[FOR_END:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[TMP0]] = insertelement <4 x float> [[LOCAL_VAR_7_0]], float 0.000000e+00, i64 2
; CHECK-NEXT: br label [[FOR_COND]]
@@ -21,7 +21,7 @@ define void @test8(i32* %inout) {
entry:
%0 = load i32, i32* %inout, align 4
%conv = uitofp i32 %0 to float
- %vecinit = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef>, float %conv, i32 3
+ %vecinit = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison>, float %conv, i32 3
%sub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %vecinit
%1 = shufflevector <4 x float> %sub, <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%mul = fmul <4 x float> zeroinitializer, %1
@@ -29,7 +29,7 @@ entry:
for.cond: ; preds = %for.body, %entry
%local_var_7.0 = phi <4 x float> [ %mul, %entry ], [ %2, %for.body ]
- br i1 undef, label %for.body, label %for.end
+ br i1 %c1, label %for.body, label %for.end
for.body: ; preds = %for.cond
%2 = insertelement <4 x float> %local_var_7.0, float 0.000000e+00, i32 2
@@ -45,7 +45,7 @@ define <vscale x 2 x float> @mul_scalable_splat_zero(<vscale x 2 x float> %z) {
; CHECK-LABEL: @mul_scalable_splat_zero(
; CHECK-NEXT: ret <vscale x 2 x float> zeroinitializer
;
- %shuf = shufflevector <vscale x 2 x float> insertelement (<vscale x 2 x float> undef, float 0.0, i32 0), <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
+ %shuf = shufflevector <vscale x 2 x float> insertelement (<vscale x 2 x float> poison, float 0.0, i32 0), <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
%t3 = fmul fast <vscale x 2 x float> %shuf, %z
ret <vscale x 2 x float> %t3
}
diff --git a/llvm/test/Transforms/InstCombine/fmul.ll b/llvm/test/Transforms/InstCombine/fmul.ll
index 97c603e80823e..33e304fb00f89 100644
--- a/llvm/test/Transforms/InstCombine/fmul.ll
+++ b/llvm/test/Transforms/InstCombine/fmul.ll
@@ -372,13 +372,13 @@ define float @unary_neg_mul_multi_use(float %x, float %y) {
}
; Don't crash when attempting to cast a constant FMul to an instruction.
-define void @test8(i32* %inout) {
+define void @test8(i32* %inout, i1 %c1) {
; CHECK-LABEL: @test8(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: [[LOCAL_VAR_7_0:%.*]] = phi <4 x float> [ <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, [[ENTRY:%.*]] ], [ [[TMP0:%.*]], [[FOR_BODY:%.*]] ]
-; CHECK-NEXT: br i1 undef, label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[FOR_BODY]], label [[FOR_END:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[TMP0]] = insertelement <4 x float> [[LOCAL_VAR_7_0]], float 0.000000e+00, i64 2
; CHECK-NEXT: br label [[FOR_COND]]
@@ -396,7 +396,7 @@ entry:
for.cond: ; preds = %for.body, %entry
%local_var_7.0 = phi <4 x float> [ %mul, %entry ], [ %2, %for.body ]
- br i1 undef, label %for.body, label %for.end
+ br i1 %c1, label %for.body, label %for.end
for.body: ; preds = %for.cond
%2 = insertelement <4 x float> %local_var_7.0, float 0.000000e+00, i32 2
diff --git a/llvm/test/Transforms/InstCombine/fold-phi.ll b/llvm/test/Transforms/InstCombine/fold-phi.ll
index df48404a09463..548286b4a8f01 100644
--- a/llvm/test/Transforms/InstCombine/fold-phi.ll
+++ b/llvm/test/Transforms/InstCombine/fold-phi.ll
@@ -1,14 +1,14 @@
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
; CHECK: no_crash
-define float @no_crash(float %a) nounwind {
+define float @no_crash(float %a, i1 %c1) nounwind {
entry:
br label %for.body
for.body:
%sum.057 = phi float [ 0.000000e+00, %entry ], [ %add5, %bb0 ]
%add5 = fadd float %sum.057, %a ; PR14592
- br i1 undef, label %bb0, label %end
+ br i1 %c1, label %bb0, label %end
bb0:
br label %for.body
@@ -18,14 +18,14 @@ end:
}
; CHECK-LABEL: @pr21377(
-define void @pr21377(i32) {
+define void @pr21377(i32, i1 %c1) {
entry:
br label %while.body
while.body: ; preds = %if.end, %entry
- %phi1 = phi i64 [ undef, %entry ], [ %or2, %if.end ]
+ %phi1 = phi i64 [ poison, %entry ], [ %or2, %if.end ]
%zext = zext i32 %0 to i64
- br i1 undef, label %if.end, label %if.else
+ br i1 %c1, label %if.end, label %if.else
if.else: ; preds = %while.body
%or1 = or i64 %phi1, %zext
@@ -33,7 +33,7 @@ if.else: ; preds = %while.body
br label %if.end
if.end: ; preds = %if.else, %while.body
- %phi2 = phi i64 [ %and, %if.else ], [ undef, %while.body ]
+ %phi2 = phi i64 [ %and, %if.else ], [ poison, %while.body ]
%or2 = or i64 %phi2, %zext
br label %while.body
}
diff --git a/llvm/test/Transforms/InstCombine/icmp-dom.ll b/llvm/test/Transforms/InstCombine/icmp-dom.ll
index 548bb68a925b9..fc4c827ca2b66 100644
--- a/llvm/test/Transforms/InstCombine/icmp-dom.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-dom.ll
@@ -34,13 +34,13 @@ lor.end:
ret void
}
-define void @idom_sign_bit_check_edge_not_dominates(i64 %a) {
+define void @idom_sign_bit_check_edge_not_dominates(i64 %a, i1 %c1) {
; CHECK-LABEL: @idom_sign_bit_check_edge_not_dominates(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[A:%.*]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[LOR_RHS:%.*]]
; CHECK: land.lhs.true:
-; CHECK-NEXT: br i1 undef, label [[LOR_END:%.*]], label [[LOR_RHS]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[LOR_END:%.*]], label [[LOR_RHS]]
; CHECK: lor.rhs:
; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[A]], 0
; CHECK-NEXT: br i1 [[CMP2]], label [[LAND_RHS:%.*]], label [[LOR_END]]
@@ -54,7 +54,7 @@ entry:
br i1 %cmp, label %land.lhs.true, label %lor.rhs
land.lhs.true:
- br i1 undef, label %lor.end, label %lor.rhs
+ br i1 %c1, label %lor.end, label %lor.rhs
lor.rhs:
%cmp2 = icmp sgt i64 %a, 0
diff --git a/llvm/test/Transforms/InstCombine/intptr6.ll b/llvm/test/Transforms/InstCombine/intptr6.ll
index 890c31092b225..e42c292cd54af 100644
--- a/llvm/test/Transforms/InstCombine/intptr6.ll
+++ b/llvm/test/Transforms/InstCombine/intptr6.ll
@@ -12,7 +12,7 @@ $foo = comdat any
declare i32 @__gxx_personality_v0(...)
; Function Attrs: inlinehint sanitize_memory uwtable
-define void @foo() local_unnamed_addr #0 comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define void @foo(i1 %c1) local_unnamed_addr #0 comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
entry:
%0 = load %C*, %C** getelementptr inbounds (%A, %A* @bar, i64 0, i32 0, i32 0), align 8
%1 = ptrtoint %C* %0 to i64
@@ -63,7 +63,7 @@ lpad15: ; preds = %invoke.cont5
ehcleanup21: ; preds = %lpad15, %ehcleanup
%actual_other.sroa.0.0 = phi i64 [ %1, %ehcleanup ], [ %4, %lpad15 ]
%8 = inttoptr i64 %actual_other.sroa.0.0 to %C*
- br i1 undef, label %_ZN4CGAL6HandleD2Ev.exit, label %land.lhs.true.i
+ br i1 %c1, label %_ZN4CGAL6HandleD2Ev.exit, label %land.lhs.true.i
land.lhs.true.i: ; preds = %ehcleanup21
%count.i = getelementptr inbounds %C, %C* %8, i64 0, i32 1
diff --git a/llvm/test/Transforms/InstCombine/load-combine-metadata-dominance.ll b/llvm/test/Transforms/InstCombine/load-combine-metadata-dominance.ll
index 40b55d9eac2a6..7a53526416a35 100644
--- a/llvm/test/Transforms/InstCombine/load-combine-metadata-dominance.ll
+++ b/llvm/test/Transforms/InstCombine/load-combine-metadata-dominance.ll
@@ -25,10 +25,10 @@ declare i32 @use(i32*, i32) readonly
; There are some cases where it would be safe to keep it.
; CHECK-LABEL: @combine_metadata_dominance2(
; CHECK-NOT: nonnull
-define void @combine_metadata_dominance2(i32** %p) {
+define void @combine_metadata_dominance2(i32** %p, i1 %c1) {
entry:
%a = load i32*, i32** %p
- br i1 undef, label %bb1, label %bb2
+ br i1 %c1, label %bb1, label %bb2
bb1:
%b = load i32*, i32** %p, !nonnull !0
diff --git a/llvm/test/Transforms/InstCombine/objsize.ll b/llvm/test/Transforms/InstCombine/objsize.ll
index 03e9ce8547d00..63df28b944887 100644
--- a/llvm/test/Transforms/InstCombine/objsize.ll
+++ b/llvm/test/Transforms/InstCombine/objsize.ll
@@ -105,30 +105,30 @@ declare i32 @llvm.objectsize.i32.p1i8(i8 addrspace(1)*, i1, i1, i1) nounwind rea
declare i8* @__inline_memcpy_chk(i8*, i8*, i32) nounwind inlinehint
-define void @test3() nounwind {
+define void @test3(i1 %c1, i8* %ptr1, i8* %ptr2, i8* %ptr3) nounwind {
; CHECK-LABEL: @test3(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 undef, label [[BB11:%.*]], label [[BB12:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB11:%.*]], label [[BB12:%.*]]
; CHECK: bb11:
; CHECK-NEXT: unreachable
; CHECK: bb12:
-; CHECK-NEXT: [[TMP0:%.*]] = call i8* @__inline_memcpy_chk(i8* bitcast (float* getelementptr inbounds ([480 x float], [480 x float]* @array, i32 0, i32 1) to i8*), i8* undef, i32 512) [[ATTR3:#.*]]
+; CHECK-NEXT: [[TMP0:%.*]] = call i8* @__inline_memcpy_chk(i8* bitcast (float* getelementptr inbounds ([480 x float], [480 x float]* @array, i32 0, i32 1) to i8*), i8* [[PTR3:%.*]], i32 512) #[[ATTR3:[0-9]+]]
; CHECK-NEXT: unreachable
;
entry:
- br i1 undef, label %bb11, label %bb12
+ br i1 %c1, label %bb11, label %bb12
bb11:
%0 = getelementptr inbounds float, float* getelementptr inbounds ([480 x float], [480 x float]* @array, i32 0, i32 128), i32 -127 ; <float*> [#uses=1]
%1 = bitcast float* %0 to i8* ; <i8*> [#uses=1]
%2 = call i32 @llvm.objectsize.i32.p0i8(i8* %1, i1 false, i1 false, i1 false) ; <i32> [#uses=1]
- %3 = call i8* @__memcpy_chk(i8* undef, i8* undef, i32 512, i32 %2) nounwind ; <i8*> [#uses=0]
+ %3 = call i8* @__memcpy_chk(i8* %ptr1, i8* %ptr2, i32 512, i32 %2) nounwind ; <i8*> [#uses=0]
unreachable
bb12:
%4 = getelementptr inbounds float, float* getelementptr inbounds ([480 x float], [480 x float]* @array, i32 0, i32 128), i32 -127 ; <float*> [#uses=1]
%5 = bitcast float* %4 to i8* ; <i8*> [#uses=1]
- %6 = call i8* @__inline_memcpy_chk(i8* %5, i8* undef, i32 512) nounwind inlinehint ; <i8*> [#uses=0]
+ %6 = call i8* @__inline_memcpy_chk(i8* %5, i8* %ptr3, i32 512) nounwind inlinehint ; <i8*> [#uses=0]
unreachable
}
@@ -141,7 +141,7 @@ define i32 @test4(i8** %esc) nounwind ssp {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_DATA:%.*]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = bitcast %struct.data* [[TMP0]] to i8*
-; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* noundef nonnull align 8 dereferenceable(1824) [[TMP1]], i8 0, i32 1824, i1 false) [[ATTR0:#.*]]
+; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* noundef nonnull align 8 dereferenceable(1824) [[TMP1]], i8 0, i32 1824, i1 false) #[[ATTR0:[0-9]+]]
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8** [[ESC:%.*]] to %struct.data**
; CHECK-NEXT: store %struct.data* [[TMP0]], %struct.data** [[TMP2]], align 4
; CHECK-NEXT: ret i32 0
@@ -161,9 +161,9 @@ entry:
define i8* @test5(i32 %n) nounwind ssp {
; CHECK-LABEL: @test5(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = tail call noalias dereferenceable_or_null(20) i8* @malloc(i32 20) [[ATTR0]]
+; CHECK-NEXT: [[TMP0:%.*]] = tail call noalias dereferenceable_or_null(20) i8* @malloc(i32 20) #[[ATTR0]]
; CHECK-NEXT: [[TMP1:%.*]] = load i8*, i8** @s, align 8
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noundef nonnull align 1 dereferenceable(10) [[TMP0]], i8* noundef nonnull align 1 dereferenceable(10) [[TMP1]], i32 10, i1 false) [[ATTR0]]
+; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* noundef nonnull align 1 dereferenceable(10) [[TMP0]], i8* noundef nonnull align 1 dereferenceable(10) [[TMP1]], i32 10, i1 false) #[[ATTR0]]
; CHECK-NEXT: ret i8* [[TMP0]]
;
entry:
@@ -177,9 +177,9 @@ entry:
define void @test6(i32 %n) nounwind ssp {
; CHECK-LABEL: @test6(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = tail call noalias dereferenceable_or_null(20) i8* @malloc(i32 20) [[ATTR0]]
+; CHECK-NEXT: [[TMP0:%.*]] = tail call noalias dereferenceable_or_null(20) i8* @malloc(i32 20) #[[ATTR0]]
; CHECK-NEXT: [[TMP1:%.*]] = load i8*, i8** @s, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = tail call i8* @__memcpy_chk(i8* [[TMP0]], i8* [[TMP1]], i32 30, i32 20) [[ATTR0]]
+; CHECK-NEXT: [[TMP2:%.*]] = tail call i8* @__memcpy_chk(i8* [[TMP0]], i8* [[TMP1]], i32 30, i32 20) #[[ATTR0]]
; CHECK-NEXT: ret void
;
entry:
@@ -196,7 +196,7 @@ declare noalias i8* @malloc(i32) nounwind
define i32 @test7(i8** %esc) {
; CHECK-LABEL: @test7(
-; CHECK-NEXT: [[ALLOC:%.*]] = call noalias dereferenceable_or_null(48) i8* @malloc(i32 48) [[ATTR0]]
+; CHECK-NEXT: [[ALLOC:%.*]] = call noalias dereferenceable_or_null(48) i8* @malloc(i32 48) #[[ATTR0]]
; CHECK-NEXT: store i8* [[ALLOC]], i8** [[ESC:%.*]], align 4
; CHECK-NEXT: ret i32 32
;
@@ -211,7 +211,7 @@ declare noalias i8* @calloc(i32, i32) nounwind
define i32 @test8(i8** %esc) {
; CHECK-LABEL: @test8(
-; CHECK-NEXT: [[ALLOC:%.*]] = call noalias dereferenceable_or_null(35) i8* @calloc(i32 5, i32 7) [[ATTR0]]
+; CHECK-NEXT: [[ALLOC:%.*]] = call noalias dereferenceable_or_null(35) i8* @calloc(i32 5, i32 7) #[[ATTR0]]
; CHECK-NEXT: store i8* [[ALLOC]], i8** [[ESC:%.*]], align 4
; CHECK-NEXT: ret i32 30
;
@@ -227,7 +227,7 @@ declare noalias i8* @strndup(i8* nocapture, i32) nounwind
define i32 @test9(i8** %esc) {
; CHECK-LABEL: @test9(
-; CHECK-NEXT: [[CALL:%.*]] = tail call dereferenceable_or_null(8) i8* @strdup(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0)) [[ATTR0]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call dereferenceable_or_null(8) i8* @strdup(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0)) #[[ATTR0]]
; CHECK-NEXT: store i8* [[CALL]], i8** [[ESC:%.*]], align 8
; CHECK-NEXT: ret i32 8
;
@@ -239,7 +239,7 @@ define i32 @test9(i8** %esc) {
define i32 @test10(i8** %esc) {
; CHECK-LABEL: @test10(
-; CHECK-NEXT: [[CALL:%.*]] = tail call dereferenceable_or_null(4) i8* @strndup(i8* dereferenceable(8) getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 3) [[ATTR0]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call dereferenceable_or_null(4) i8* @strndup(i8* dereferenceable(8) getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 3) #[[ATTR0]]
; CHECK-NEXT: store i8* [[CALL]], i8** [[ESC:%.*]], align 8
; CHECK-NEXT: ret i32 4
;
diff --git a/llvm/test/Transforms/InstCombine/oss_fuzz_32759.ll b/llvm/test/Transforms/InstCombine/oss_fuzz_32759.ll
index 7fc5f648f6a01..9f6db50d0c4bb 100644
--- a/llvm/test/Transforms/InstCombine/oss_fuzz_32759.ll
+++ b/llvm/test/Transforms/InstCombine/oss_fuzz_32759.ll
@@ -2,17 +2,17 @@
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
target datalayout = "n32"
-define i1 @oss_fuzz_32759(i1 %y) {
+define i1 @oss_fuzz_32759(i1 %y, i1 %c1) {
; CHECK-LABEL: @oss_fuzz_32759(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 undef, label [[COND_TRUE:%.*]], label [[END:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[COND_TRUE:%.*]], label [[END:%.*]]
; CHECK: cond.true:
; CHECK-NEXT: br label [[END]]
; CHECK: end:
; CHECK-NEXT: ret i1 false
;
entry:
- br i1 undef, label %cond.true, label %end
+ br i1 %c1, label %cond.true, label %end
cond.true: ; preds = %entry
%zy = zext i1 %y to i32
diff --git a/llvm/test/Transforms/InstCombine/pr51824.ll b/llvm/test/Transforms/InstCombine/pr51824.ll
index 557512a5f18c9..bd926439260c6 100644
--- a/llvm/test/Transforms/InstCombine/pr51824.ll
+++ b/llvm/test/Transforms/InstCombine/pr51824.ll
@@ -2,12 +2,12 @@
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
; OSS-Fuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=38057
-define void @PR51824() {
+define void @PR51824(<4 x i16> %idxs, i32* %ptr, i1 %c1, <4 x i32>* %ptr2) {
; CHECK-LABEL: @PR51824(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: BB:
-; CHECK-NEXT: br i1 undef, label [[BB]], label [[BB1:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB]], label [[BB1:%.*]]
; CHECK: BB1:
; CHECK-NEXT: ret void
;
@@ -16,7 +16,7 @@ entry:
%B2 = lshr i16 -32768, 0
%C1 = icmp uge i16 %B2, %B2
%E9 = extractelement <4 x i16> zeroinitializer, i16 %B2
- %I2 = insertelement <4 x i16> undef, i16 %E9, i16 0
+ %I2 = insertelement <4 x i16> poison, i16 %E9, i16 0
%i = sext <4 x i16> %I2 to <4 x i32>
%i1 = getelementptr inbounds i64, i64* null, <4 x i32> %i
%i2 = ptrtoint <4 x i64*> %i1 to <4 x i32>
@@ -27,20 +27,20 @@ BB: ; preds = %BB, %entry
%A15 = alloca <4 x i32>, align 16
%L2 = load <4 x i32>, <4 x i32>* %A15, align 16
%G1 = getelementptr i64, i64* null, i32 %E2
- %i3 = getelementptr inbounds i64, i64* %G1, <4 x i16> undef
+ %i3 = getelementptr inbounds i64, i64* %G1, <4 x i16> %idxs
%i4 = ptrtoint <4 x i64*> %i3 to <4 x i32>
%E22 = extractelement <4 x i32> %L2, i1 false
%E8 = extractelement <4 x i32> %i4, i1 false
%I10 = insertelement <4 x i32> undef, i32 undef, i32 %E8
%I19 = insertelement <4 x i32> %I10, i32 %E22, i16 0
- %S7 = shufflevector <4 x i32> %I19, <4 x i32> %L2, <4 x i32> undef
+ %S7 = shufflevector <4 x i32> %I19, <4 x i32> %L2, <4 x i32> poison
%I8 = insertelement <4 x i32> %I19, i32 0, i1 %C1
- %E10 = extractelement <4 x i32> %I8, i1 undef
- store i32 %E10, i32* undef, align 4
- br i1 undef, label %BB, label %BB1
+ %E10 = extractelement <4 x i32> %I8, i1 poison
+ store i32 %E10, i32* %ptr, align 4
+ br i1 %c1, label %BB, label %BB1
BB1: ; preds = %BB
%S8 = shufflevector <4 x i32> %I10, <4 x i32> %S7, <4 x i32> undef
- store <4 x i32> %S8, <4 x i32>* undef, align 16
+ store <4 x i32> %S8, <4 x i32>* %ptr2, align 16
ret void
}
diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index b5f8c3a4b7cfe..0af3fe523f476 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -41,12 +41,12 @@ define <2 x i1> @trueval_is_true_vec(<2 x i1> %C, <2 x i1> %X) {
ret <2 x i1> %R
}
-define <2 x i1> @trueval_is_true_vec_undef_elt(<2 x i1> %C, <2 x i1> %X) {
-; CHECK-LABEL: @trueval_is_true_vec_undef_elt(
-; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i1> <i1 undef, i1 true>, <2 x i1> [[X:%.*]]
+define <2 x i1> @trueval_is_true_vec_poison_elt(<2 x i1> %C, <2 x i1> %X) {
+; CHECK-LABEL: @trueval_is_true_vec_poison_elt(
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i1> <i1 poison, i1 true>, <2 x i1> [[X:%.*]]
; CHECK-NEXT: ret <2 x i1> [[R]]
;
- %R = select <2 x i1> %C, <2 x i1> <i1 undef, i1 true>, <2 x i1> %X
+ %R = select <2 x i1> %C, <2 x i1> <i1 poison, i1 true>, <2 x i1> %X
ret <2 x i1> %R
}
@@ -958,10 +958,10 @@ define i32 @test61(i32* %ptr) {
}
; PR14131
-define void @test64(i32 %p, i16 %b) noreturn {
+define void @test64(i32 %p, i16 %b, i1 %c1) noreturn {
; CHECK-LABEL: @test64(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 undef, label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
; CHECK: lor.rhs:
; CHECK-NEXT: br label [[LOR_END]]
; CHECK: lor.end:
@@ -976,7 +976,7 @@ define void @test64(i32 %p, i16 %b) noreturn {
entry:
%p.addr.0.insert.mask = and i32 %p, -65536
%conv2 = and i32 %p, 65535
- br i1 undef, label %lor.rhs, label %lor.end
+ br i1 %c1, label %lor.rhs, label %lor.end
lor.rhs:
%p.addr.0.extract.trunc = trunc i32 %p.addr.0.insert.mask to i16
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-shl.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-shl.ll
index 1fe051790b2eb..d2d07687899eb 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-shl.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-shl.ll
@@ -59,13 +59,13 @@ define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {
; Basic vector tests
-define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
-; CHECK-LABEL: @t3_vec_nonsplat_undef0(
+define <3 x i16> @t3_vec_nonsplat_poison0(<3 x i32> %x, <3 x i16> %y) {
+; CHECK-LABEL: @t3_vec_nonsplat_poison0(
; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
-; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 poison, i16 8>
; CHECK-NEXT: ret <3 x i16> [[T5]]
;
- %t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
+ %t0 = sub <3 x i16> <i16 32, i16 poison, i16 32>, %y
%t1 = zext <3 x i16> %t0 to <3 x i32>
%t2 = shl <3 x i32> %x, %t1
%t3 = trunc <3 x i32> %t2 to <3 x i16>
@@ -74,32 +74,32 @@ define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
ret <3 x i16> %t5
}
-define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
-; CHECK-LABEL: @t4_vec_nonsplat_undef1(
+define <3 x i16> @t4_vec_nonsplat_poison1(<3 x i32> %x, <3 x i16> %y) {
+; CHECK-LABEL: @t4_vec_nonsplat_poison1(
; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
-; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 poison, i16 8>
; CHECK-NEXT: ret <3 x i16> [[T5]]
;
%t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y
%t1 = zext <3 x i16> %t0 to <3 x i32>
%t2 = shl <3 x i32> %x, %t1
%t3 = trunc <3 x i32> %t2 to <3 x i16>
- %t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
+ %t4 = add <3 x i16> %y, <i16 -24, i16 poison, i16 -24>
%t5 = shl <3 x i16> %t3, %t4
ret <3 x i16> %t5
}
-define <3 x i16> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
-; CHECK-LABEL: @t5_vec_nonsplat_undef1(
+define <3 x i16> @t5_vec_nonsplat_poison1(<3 x i32> %x, <3 x i16> %y) {
+; CHECK-LABEL: @t5_vec_nonsplat_poison1(
; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
-; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 poison, i16 8>
; CHECK-NEXT: ret <3 x i16> [[T5]]
;
- %t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
+ %t0 = sub <3 x i16> <i16 32, i16 poison, i16 32>, %y
%t1 = zext <3 x i16> %t0 to <3 x i32>
%t2 = shl <3 x i32> %x, %t1
%t3 = trunc <3 x i32> %t2 to <3 x i16>
- %t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
+ %t4 = add <3 x i16> %y, <i16 -24, i16 poison, i16 -24>
%t5 = shl <3 x i16> %t3, %t4
ret <3 x i16> %t5
}
@@ -235,17 +235,17 @@ define i16 @shl_tr_shl_constant_shift_amount_uses(i32 %x) {
; the problematic transform, it needs a datalayout to specify
; that the narrow types are legal, but i64 is not.
-define i1 @PR51657(i64 %x) {
+define i1 @PR51657(i64 %x, i1 %c1) {
; CHECK-LABEL: @PR51657(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 undef, label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
; CHECK: cond.false:
; CHECK-NEXT: br label [[COND_END]]
; CHECK: cond.end:
; CHECK-NEXT: ret i1 true
;
entry:
- br i1 undef, label %cond.false, label %cond.end
+ br i1 %c1, label %cond.false, label %cond.end
cond.false:
%shl = shl i64 %x, 64
diff --git a/llvm/test/Transforms/InstCombine/shift-sra.ll b/llvm/test/Transforms/InstCombine/shift-sra.ll
index cf7e39840c846..34afdddedb189 100644
--- a/llvm/test/Transforms/InstCombine/shift-sra.ll
+++ b/llvm/test/Transforms/InstCombine/shift-sra.ll
@@ -4,8 +4,8 @@
define i32 @test1(i32 %X, i8 %A) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext i8 %A to i32
-; CHECK-NEXT: [[Y1:%.*]] = lshr i32 %X, [[SHIFT_UPGRD_1]]
+; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext i8 [[A:%.*]] to i32
+; CHECK-NEXT: [[Y1:%.*]] = lshr i32 [[X:%.*]], [[SHIFT_UPGRD_1]]
; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y1]], 1
; CHECK-NEXT: ret i32 [[Z]]
;
@@ -16,30 +16,30 @@ define i32 @test1(i32 %X, i8 %A) {
ret i32 %Z
}
-define i32 @test2(i8 %tmp) {
+define i32 @test2(i8 %a) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[TMP3:%.*]] = zext i8 %tmp to i32
-; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 7
-; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP4]], 3
+; CHECK-NEXT: [[B:%.*]] = zext i8 [[A:%.*]] to i32
+; CHECK-NEXT: [[C:%.*]] = add nuw nsw i32 [[B]], 7
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[C]], 3
; CHECK-NEXT: ret i32 [[TMP1]]
;
- %tmp3 = zext i8 %tmp to i32
- %tmp4 = add i32 %tmp3, 7
- %tmp5 = ashr i32 %tmp4, 3
- ret i32 %tmp5
+ %b = zext i8 %a to i32
+ %c = add i32 %b, 7
+ %d = ashr i32 %c, 3
+ ret i32 %d
}
define i64 @test3(i1 %X, i64 %Y, i1 %Cond) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: br i1 %Cond, label %T, label %F
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
; CHECK: T:
-; CHECK-NEXT: [[X2:%.*]] = sext i1 %X to i64
-; CHECK-NEXT: br label %C
+; CHECK-NEXT: [[X2:%.*]] = sext i1 [[X:%.*]] to i64
+; CHECK-NEXT: br label [[C:%.*]]
; CHECK: F:
-; CHECK-NEXT: [[Y2:%.*]] = ashr i64 %Y, 63
-; CHECK-NEXT: br label %C
+; CHECK-NEXT: [[Y2:%.*]] = ashr i64 [[Y:%.*]], 63
+; CHECK-NEXT: br label [[C]]
; CHECK: C:
-; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[X2]], %T ], [ [[Y2]], %F ]
+; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[X2]], [[T]] ], [ [[Y2]], [[F]] ]
; CHECK-NEXT: ret i64 [[P]]
;
br i1 %Cond, label %T, label %F
@@ -57,15 +57,15 @@ C:
define i64 @test4(i1 %X, i64 %Y, i1 %Cond) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: br i1 %Cond, label %T, label %F
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
; CHECK: T:
-; CHECK-NEXT: [[X2:%.*]] = sext i1 %X to i64
-; CHECK-NEXT: br label %C
+; CHECK-NEXT: [[X2:%.*]] = sext i1 [[X:%.*]] to i64
+; CHECK-NEXT: br label [[C:%.*]]
; CHECK: F:
-; CHECK-NEXT: [[Y2:%.*]] = ashr i64 %Y, 63
-; CHECK-NEXT: br label %C
+; CHECK-NEXT: [[Y2:%.*]] = ashr i64 [[Y:%.*]], 63
+; CHECK-NEXT: br label [[C]]
; CHECK: C:
-; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[X2]], %T ], [ [[Y2]], %F ]
+; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[X2]], [[T]] ], [ [[Y2]], [[F]] ]
; CHECK-NEXT: ret i64 [[P]]
;
br i1 %Cond, label %T, label %F
@@ -83,29 +83,29 @@ C:
}
; rdar://7732987
-define i32 @test5(i32 %Y) {
+define i32 @test5(i32 %Y, i1 %c1, i1 %c2, i1 %c3) {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: br i1 undef, label %A, label %C
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[A:%.*]], label [[C:%.*]]
; CHECK: A:
-; CHECK-NEXT: br i1 undef, label %B, label %D
+; CHECK-NEXT: br i1 [[C2:%.*]], label [[B:%.*]], label [[D:%.*]]
; CHECK: B:
-; CHECK-NEXT: br label %D
+; CHECK-NEXT: br label [[D]]
; CHECK: C:
-; CHECK-NEXT: br i1 undef, label %D, label %E
+; CHECK-NEXT: br i1 [[C3:%.*]], label [[D]], label [[E:%.*]]
; CHECK: D:
-; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, %A ], [ 0, %B ], [ %Y, %C ]
+; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, [[A]] ], [ 0, [[B]] ], [ [[Y:%.*]], [[C]] ]
; CHECK-NEXT: [[S:%.*]] = ashr i32 [[P]], 16
; CHECK-NEXT: ret i32 [[S]]
; CHECK: E:
; CHECK-NEXT: ret i32 0
;
- br i1 undef, label %A, label %C
+ br i1 %c1, label %A, label %C
A:
- br i1 undef, label %B, label %D
+ br i1 %c2, label %B, label %D
B:
br label %D
C:
- br i1 undef, label %D, label %E
+ br i1 %c3, label %D, label %E
D:
%P = phi i32 [0, %A], [0, %B], [%Y, %C]
%S = ashr i32 %P, 16
@@ -118,7 +118,7 @@ E:
define i32 @ashr_ashr(i32 %x) {
; CHECK-LABEL: @ashr_ashr(
-; CHECK-NEXT: [[SH2:%.*]] = ashr i32 %x, 12
+; CHECK-NEXT: [[SH2:%.*]] = ashr i32 [[X:%.*]], 12
; CHECK-NEXT: ret i32 [[SH2]]
;
%sh1 = ashr i32 %x, 5
@@ -131,7 +131,7 @@ define i32 @ashr_ashr(i32 %x) {
define i32 @ashr_overshift(i32 %x) {
; CHECK-LABEL: @ashr_overshift(
-; CHECK-NEXT: [[SH2:%.*]] = ashr i32 %x, 31
+; CHECK-NEXT: [[SH2:%.*]] = ashr i32 [[X:%.*]], 31
; CHECK-NEXT: ret i32 [[SH2]]
;
%sh1 = ashr i32 %x, 15
@@ -143,7 +143,7 @@ define i32 @ashr_overshift(i32 %x) {
define <2 x i32> @ashr_ashr_splat_vec(<2 x i32> %x) {
; CHECK-LABEL: @ashr_ashr_splat_vec(
-; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> %x, <i32 12, i32 12>
+; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 12, i32 12>
; CHECK-NEXT: ret <2 x i32> [[SH2]]
;
%sh1 = ashr <2 x i32> %x, <i32 5, i32 5>
@@ -155,7 +155,7 @@ define <2 x i32> @ashr_ashr_splat_vec(<2 x i32> %x) {
define <2 x i32> @ashr_overshift_splat_vec(<2 x i32> %x) {
; CHECK-LABEL: @ashr_overshift_splat_vec(
-; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> %x, <i32 31, i32 31>
+; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 31, i32 31>
; CHECK-NEXT: ret <2 x i32> [[SH2]]
;
%sh1 = ashr <2 x i32> %x, <i32 15, i32 15>
@@ -167,7 +167,7 @@ define <2 x i32> @ashr_overshift_splat_vec(<2 x i32> %x) {
define i32 @hoist_ashr_ahead_of_sext_1(i8 %x) {
; CHECK-LABEL: @hoist_ashr_ahead_of_sext_1(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 3
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 [[X:%.*]], 3
; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[R]]
;
@@ -180,7 +180,7 @@ define i32 @hoist_ashr_ahead_of_sext_1(i8 %x) {
define <2 x i32> @hoist_ashr_ahead_of_sext_1_splat(<2 x i8> %x) {
; CHECK-LABEL: @hoist_ashr_ahead_of_sext_1_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i8> %x, <i8 3, i8 3>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 3, i8 3>
; CHECK-NEXT: [[R:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[R]]
;
@@ -193,7 +193,7 @@ define <2 x i32> @hoist_ashr_ahead_of_sext_1_splat(<2 x i8> %x) {
define i32 @hoist_ashr_ahead_of_sext_2(i8 %x) {
; CHECK-LABEL: @hoist_ashr_ahead_of_sext_2(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 7
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 [[X:%.*]], 7
; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[R]]
;
@@ -206,7 +206,7 @@ define i32 @hoist_ashr_ahead_of_sext_2(i8 %x) {
define <2 x i32> @hoist_ashr_ahead_of_sext_2_splat(<2 x i8> %x) {
; CHECK-LABEL: @hoist_ashr_ahead_of_sext_2_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7>
; CHECK-NEXT: [[R:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[R]]
;
diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 5855c684ca397..28b5091b3a711 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -456,18 +456,18 @@ entry:
ret <2 x i32> %i10
}
-define <2 x i32> @test29_undef(<2 x i64> %d18) {
-; CHECK-LABEL: @test29_undef(
+define <2 x i32> @test29_poison(<2 x i64> %d18) {
+; CHECK-LABEL: @test29_poison(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[I916:%.*]] = lshr <2 x i64> [[D18:%.*]], <i64 32, i64 undef>
+; CHECK-NEXT: [[I916:%.*]] = lshr <2 x i64> [[D18:%.*]], <i64 32, i64 poison>
; CHECK-NEXT: [[I917:%.*]] = trunc <2 x i64> [[I916]] to <2 x i32>
-; CHECK-NEXT: [[I10:%.*]] = lshr <2 x i32> [[I917]], <i32 31, i32 undef>
+; CHECK-NEXT: [[I10:%.*]] = lshr <2 x i32> [[I917]], <i32 31, i32 poison>
; CHECK-NEXT: ret <2 x i32> [[I10]]
;
entry:
- %i916 = lshr <2 x i64> %d18, <i64 32, i64 undef>
+ %i916 = lshr <2 x i64> %d18, <i64 32, i64 poison>
%i917 = trunc <2 x i64> %i916 to <2 x i32>
- %i10 = lshr <2 x i32> %i917, <i32 31, i32 undef>
+ %i10 = lshr <2 x i32> %i917, <i32 31, i32 poison>
ret <2 x i32> %i10
}
@@ -632,11 +632,11 @@ define <3 x i32> @test38_nonuniform(<3 x i32> %x) nounwind readnone {
ret <3 x i32> %shl
}
-define <2 x i32> @test38_undef(<2 x i32> %x) nounwind readnone {
-; CHECK-LABEL: @test38_undef(
+define <2 x i32> @test38_poison(<2 x i32> %x) nounwind readnone {
+; CHECK-LABEL: @test38_poison(
; CHECK-NEXT: ret <2 x i32> poison
;
- %rem = srem <2 x i32> %x, <i32 32, i32 undef>
+ %rem = srem <2 x i32> %x, <i32 32, i32 poison>
%shl = shl <2 x i32> <i32 1, i32 1>, %rem
ret <2 x i32> %shl
}
@@ -1106,51 +1106,51 @@ define i32 @test60(i32 %x) {
}
; PR17026
-define void @test61(i128 %arg) {
+define void @test61(i128 %arg, i1 %c1, i1 %c2, i1 %c3, i1 %c4) {
; CHECK-LABEL: @test61(
; CHECK-NEXT: bb:
-; CHECK-NEXT: br i1 undef, label [[BB1:%.*]], label [[BB12:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB12:%.*]]
; CHECK: bb1:
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: br i1 undef, label [[BB3:%.*]], label [[BB7:%.*]]
+; CHECK-NEXT: br i1 [[C2:%.*]], label [[BB3:%.*]], label [[BB7:%.*]]
; CHECK: bb3:
; CHECK-NEXT: br label [[BB8:%.*]]
; CHECK: bb7:
-; CHECK-NEXT: br i1 undef, label [[BB8]], label [[BB2]]
+; CHECK-NEXT: br i1 [[C3:%.*]], label [[BB8]], label [[BB2]]
; CHECK: bb8:
; CHECK-NEXT: br i1 undef, label [[BB11:%.*]], label [[BB12]]
; CHECK: bb11:
-; CHECK-NEXT: br i1 undef, label [[BB1]], label [[BB12]]
+; CHECK-NEXT: br i1 [[C4:%.*]], label [[BB1]], label [[BB12]]
; CHECK: bb12:
; CHECK-NEXT: ret void
;
bb:
- br i1 undef, label %bb1, label %bb12
+ br i1 %c1, label %bb1, label %bb12
bb1: ; preds = %bb11, %bb
br label %bb2
bb2: ; preds = %bb7, %bb1
- br i1 undef, label %bb3, label %bb7
+ br i1 %c2, label %bb3, label %bb7
bb3: ; preds = %bb2
%i = lshr i128 %arg, 36893488147419103232
%i4 = shl i128 %i, 0
- %i5 = or i128 %i4, undef
+ %i5 = or i128 %i4, 0
%i6 = trunc i128 %i5 to i16
br label %bb8
bb7: ; preds = %bb2
- br i1 undef, label %bb8, label %bb2
+ br i1 %c3, label %bb8, label %bb2
bb8: ; preds = %bb7, %bb3
- %i9 = phi i16 [ %i6, %bb3 ], [ undef, %bb7 ]
+ %i9 = phi i16 [ %i6, %bb3 ], [ poison, %bb7 ]
%i10 = icmp eq i16 %i9, 0
br i1 %i10, label %bb11, label %bb12
bb11: ; preds = %bb8
- br i1 undef, label %bb1, label %bb12
+ br i1 %c4, label %bb1, label %bb12
bb12: ; preds = %bb11, %bb8, %bb
ret void
@@ -1641,14 +1641,14 @@ define i32 @ashr_select_xor_false(i32 %x, i1 %cond) {
; OSS Fuzz #4871
; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4871
-define i177 @lshr_out_of_range(i177 %Y, i177** %A2) {
+define i177 @lshr_out_of_range(i177 %Y, i177** %A2, i177*** %ptr) {
; CHECK-LABEL: @lshr_out_of_range(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i177 [[Y:%.*]], -1
; CHECK-NEXT: [[B4:%.*]] = sext i1 [[TMP1]] to i177
; CHECK-NEXT: [[C8:%.*]] = icmp ult i177 [[B4]], [[Y]]
; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[C8]] to i64
; CHECK-NEXT: [[G18:%.*]] = getelementptr i177*, i177** [[A2:%.*]], i64 [[TMP2]]
-; CHECK-NEXT: store i177** [[G18]], i177*** undef, align 8
+; CHECK-NEXT: store i177** [[G18]], i177*** [[PTR:%.*]], align 8
; CHECK-NEXT: ret i177 0
;
%B5 = udiv i177 %Y, -1
@@ -1660,14 +1660,14 @@ define i177 @lshr_out_of_range(i177 %Y, i177** %A2) {
%B12 = lshr i177 %Y, %B6
%C8 = icmp ugt i177 %B12, %B4
%G18 = getelementptr i177*, i177** %A2, i1 %C8
- store i177** %G18, i177*** undef
+ store i177** %G18, i177*** %ptr
%B1 = udiv i177 %B10, %B6
ret i177 %B1
}
; OSS Fuzz #26716
; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=26716
-define i177 @lshr_out_of_range2(i177 %Y, i177** %A2) {
+define i177 @lshr_out_of_range2(i177 %Y, i177** %A2, i177*** %ptr) {
; CHECK-LABEL: @lshr_out_of_range2(
; CHECK-NEXT: ret i177 0
;
@@ -1679,7 +1679,7 @@ define i177 @lshr_out_of_range2(i177 %Y, i177** %A2) {
%B12 = lshr i177 %Y, %B6
%C8 = icmp ugt i177 %B12, %B4
%G18 = getelementptr i177*, i177** %A2, i1 %C8
- store i177** %G18, i177*** undef, align 8
+ store i177** %G18, i177*** %ptr, align 8
%B1 = udiv i177 %B5, %B6
ret i177 %B1
}
@@ -1747,13 +1747,14 @@ define void @ashr_out_of_range_1(i177* %A) {
; OSS Fuzz #38078
; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=38078
-define void @ossfuzz_38078(i32 %arg, i32 %arg1) {
+define void @ossfuzz_38078(i32 %arg, i32 %arg1, i32* %ptr, i1* %ptr2, i32* %ptr3, i1* %ptr4, i32* %ptr5, i32* %ptr6, i1* %ptr7) {
; CHECK-LABEL: @ossfuzz_38078(
; CHECK-NEXT: bb:
+; CHECK-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], i64 -1
; CHECK-NEXT: [[I2:%.*]] = sub i32 0, [[ARG1:%.*]]
; CHECK-NEXT: [[I5:%.*]] = icmp eq i32 [[I2]], [[ARG:%.*]]
; CHECK-NEXT: call void @llvm.assume(i1 [[I5]])
-; CHECK-NEXT: store volatile i32 undef, i32* undef, align 4
+; CHECK-NEXT: store volatile i32 2147483647, i32* [[G1]], align 4
; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: BB:
; CHECK-NEXT: unreachable
@@ -1782,27 +1783,27 @@ bb:
%C2 = icmp sge i1 %C1, false
%C7 = icmp sle i32 %i3, %B16
%B20 = xor i32 %B21, %B22
- %G1 = getelementptr i32, i32* undef, i32 %B22
- %B1 = sub i32 %B, undef
- %B26 = ashr i32 %B29, undef
- %B4 = add i32 undef, %B5
+ %G1 = getelementptr i32, i32* %ptr, i32 %B22
+ %B1 = sub i32 %B, 0
+ %B26 = ashr i32 %B29, 0
+ %B4 = add i32 0, %B5
%B27 = srem i32 %B12, %B21
%i5 = icmp eq i32 %B20, %B18
%C11 = icmp ugt i32 %i4, %B4
call void @llvm.assume(i1 %i5)
store volatile i32 %B4, i32* %G1, align 4
- %B11 = or i32 undef, %B23
+ %B11 = or i32 0, %B23
br label %BB
BB:
- store i1 %C7, i1* undef, align 1
- store i32 %B11, i32* undef, align 4
- store i1 %C11, i1* undef, align 1
- store i32 %B1, i32* undef, align 4
- store i32 %B27, i32* undef, align 4
- %C = icmp ne i32 %B26, undef
+ store i1 %C7, i1* %ptr2, align 1
+ store i32 %B11, i32* %ptr3, align 4
+ store i1 %C11, i1* %ptr4, align 1
+ store i32 %B1, i32* %ptr5, align 4
+ store i32 %B27, i32* %ptr6, align 4
+ %C = icmp ne i32 %B26, 0
%B17 = or i1 %C, %C2
- store i1 %B17, i1* undef, align 1
+ store i1 %B17, i1* %ptr7, align 1
unreachable
}
declare void @llvm.assume(i1 noundef)
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll
index 4d6ea73bce1a0..6e8cc6c0c2020 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll
@@ -15,30 +15,30 @@ target triple = "x86_64-unknown-linux-gnu"
%struct.u = type { %struct.block_symbol }
%struct.unnamed_section = type { %struct.omp_clause_subcode, void (i8*)*, i8*, %struct.section* }
-define fastcc void @cse_insn(%struct.rtx_def* %insn, %struct.rtx_def* %libcall_insn) nounwind {
+define fastcc void @cse_insn(%struct.rtx_def* %insn, %struct.rtx_def* %libcall_insn, i16* %ptr, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9) nounwind {
entry:
- br i1 undef, label %bb43, label %bb88
+ br i1 %c1, label %bb43, label %bb88
bb43: ; preds = %entry
br label %bb88
bb88: ; preds = %bb43, %entry
- br i1 undef, label %bb95, label %bb107
+ br i1 %c2, label %bb95, label %bb107
bb95: ; preds = %bb88
unreachable
bb107: ; preds = %bb88
- %0 = load i16, i16* undef, align 8 ; <i16> [#uses=1]
+ %0 = load i16, i16* %ptr, align 8 ; <i16> [#uses=1]
%1 = icmp eq i16 %0, 38 ; <i1> [#uses=1]
%src_eqv_here.0 = select i1 %1, %struct.rtx_def* null, %struct.rtx_def* null ; <%struct.rtx_def*> [#uses=1]
- br i1 undef, label %bb127, label %bb125
+ br i1 %c3, label %bb127, label %bb125
bb125: ; preds = %bb107
- br i1 undef, label %bb127, label %bb126
+ br i1 %c4, label %bb127, label %bb126
bb126: ; preds = %bb125
- br i1 undef, label %bb129, label %bb133
+ br i1 %c5, label %bb129, label %bb133
bb127: ; preds = %bb125, %bb107
unreachable
@@ -47,13 +47,13 @@ bb129: ; preds = %bb126
br label %bb133
bb133: ; preds = %bb129, %bb126
- br i1 undef, label %bb134, label %bb146
+ br i1 %c6, label %bb134, label %bb146
bb134: ; preds = %bb133
unreachable
bb146: ; preds = %bb133
- br i1 undef, label %bb180, label %bb186
+ br i1 %c7, label %bb180, label %bb186
bb180: ; preds = %bb146
%2 = icmp eq %struct.rtx_def* null, null ; <i1> [#uses=1]
@@ -68,13 +68,13 @@ bb180: ; preds = %bb146
br i1 %toBool183, label %bb184, label %bb186
bb184: ; preds = %bb180
- br i1 undef, label %bb185, label %bb186
+ br i1 %c8, label %bb185, label %bb186
bb185: ; preds = %bb184
br label %bb186
bb186: ; preds = %bb185, %bb184, %bb180, %bb146
- br i1 undef, label %bb190, label %bb195
+ br i1 %c9, label %bb190, label %bb195
bb190: ; preds = %bb186
unreachable
diff --git a/llvm/test/Transforms/InstCombine/simplify-libcalls.ll b/llvm/test/Transforms/InstCombine/simplify-libcalls.ll
index 4746587353fb8..2964d6c29d7bd 100644
--- a/llvm/test/Transforms/InstCombine/simplify-libcalls.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-libcalls.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S < %s -mtriple=unknown -passes=instcombine -instcombine-infinite-loop-threshold=2 | FileCheck -check-prefixes=CHECK,CHECK32 %s
; RUN: opt -S < %s -mtriple=msp430 -passes=instcombine -instcombine-infinite-loop-threshold=2 | FileCheck -check-prefixes=CHECK,CHECK16 %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
@@ -7,8 +8,13 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
declare i32 @sprintf(i8*, i8*, ...)
define void @foo(i8* %P, i32* %X) {
- call i32 (i8*, i8*, ...) @sprintf( i8* %P, i8* getelementptr ([3 x i8], [3 x i8]* @G, i32 0, i32 0), i32* %X ) ; <i32>:1 [#uses=0]
- ret void
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: [[CSTR:%.*]] = bitcast i32* [[X:%.*]] to i8*
+; CHECK-NEXT: [[STRCPY:%.*]] = call i8* @strcpy(i8* noundef nonnull dereferenceable(1) [[P:%.*]], i8* noundef nonnull dereferenceable(1) [[CSTR]])
+; CHECK-NEXT: ret void
+;
+ call i32 (i8*, i8*, ...) @sprintf( i8* %P, i8* getelementptr ([3 x i8], [3 x i8]* @G, i32 0, i32 0), i32* %X ) ; <i32>:1 [#uses=0]
+ ret void
}
; PR1307
@@ -17,30 +23,32 @@ define void @foo(i8* %P, i32* %X) {
@str2 = internal constant [5 x i8] c"Ponk\00"
define i8* @test1() {
- %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8], [5 x i8]* @str, i32 0, i32 2), i32 103 ) ; <i8*> [#uses=1]
- ret i8* %tmp3
-
; CHECK-LABEL: @test1(
-; CHECK: ret i8* getelementptr inbounds ([5 x i8], [5 x i8]* @str, i32 0, i32 3)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([5 x i8], [5 x i8]* @str, i32 0, i32 3)
+;
+ %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8], [5 x i8]* @str, i32 0, i32 2), i32 103 ) ; <i8*> [#uses=1]
+ ret i8* %tmp3
}
declare i8* @strchr(i8*, i32)
define i8* @test2() {
- %tmp3 = tail call i8* @strchr( i8* getelementptr ([8 x i8], [8 x i8]* @str1, i32 0, i32 2), i32 0 ) ; <i8*> [#uses=1]
- ret i8* %tmp3
-
; CHECK-LABEL: @test2(
-; CHECK: ret i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 7)
+; CHECK-NEXT: ret i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 7)
+;
+ %tmp3 = tail call i8* @strchr( i8* getelementptr ([8 x i8], [8 x i8]* @str1, i32 0, i32 2), i32 0 ) ; <i8*> [#uses=1]
+ ret i8* %tmp3
}
define i8* @test3() {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret i8* null
+;
entry:
- %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8], [5 x i8]* @str2, i32 0, i32 1), i32 80 ) ; <i8*> [#uses=1]
- ret i8* %tmp3
+ %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8], [5 x i8]* @str2, i32 0, i32 1), i32 80 ) ; <i8*> [#uses=1]
+ ret i8* %tmp3
-; CHECK-LABEL: @test3(
-; CHECK: ret i8* null
}
@_2E_str = external constant [5 x i8] ; <[5 x i8]*> [#uses=1]
@@ -48,27 +56,34 @@ entry:
declare i32 @memcmp(i8*, i8*, i32) nounwind readonly
define i1 @PR2341(i8** %start_addr) {
+; CHECK-LABEL: @PR2341(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = load i8*, i8** [[START_ADDR:%.*]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = call i32 @memcmp(i8* noundef nonnull dereferenceable(4) [[TMP4]], i8* noundef nonnull dereferenceable(4) getelementptr inbounds ([5 x i8], [5 x i8]* @_2E_str, i32 0, i32 0), i32 4) #[[ATTR0:[0-9]+]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT: ret i1 [[TMP6]]
+;
entry:
- %tmp4 = load i8*, i8** %start_addr, align 4 ; <i8*> [#uses=1]
- %tmp5 = call i32 @memcmp( i8* %tmp4, i8* getelementptr ([5 x i8], [5 x i8]* @_2E_str, i32 0, i32 0), i32 4 ) nounwind readonly ; <i32> [#uses=1]
- %tmp6 = icmp eq i32 %tmp5, 0 ; <i1> [#uses=1]
- ret i1 %tmp6
+ %tmp4 = load i8*, i8** %start_addr, align 4 ; <i8*> [#uses=1]
+ %tmp5 = call i32 @memcmp( i8* %tmp4, i8* getelementptr ([5 x i8], [5 x i8]* @_2E_str, i32 0, i32 0), i32 4 ) nounwind readonly ; <i32> [#uses=1]
+ %tmp6 = icmp eq i32 %tmp5, 0 ; <i1> [#uses=1]
+ ret i1 %tmp6
-; CHECK-LABEL: @PR2341(
-; CHECK: i32
}
define i32 @PR4284() nounwind {
+; CHECK-LABEL: @PR4284(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret i32 -65
+;
entry:
- %c0 = alloca i8, align 1 ; <i8*> [#uses=2]
- %c2 = alloca i8, align 1 ; <i8*> [#uses=2]
- store i8 64, i8* %c0
- store i8 -127, i8* %c2
- %call = call i32 @memcmp(i8* %c0, i8* %c2, i32 1) ; <i32> [#uses=1]
- ret i32 %call
+ %c0 = alloca i8, align 1 ; <i8*> [#uses=2]
+ %c2 = alloca i8, align 1 ; <i8*> [#uses=2]
+ store i8 64, i8* %c0
+ store i8 -127, i8* %c2
+ %call = call i32 @memcmp(i8* %c0, i8* %c2, i32 1) ; <i32> [#uses=1]
+ ret i32 %call
-; CHECK-LABEL: @PR4284(
-; CHECK: ret i32 -65
}
%struct.__sFILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64, %struct.pthread_mutex*, %struct.pthread*, i32, i32, %union.anon }
@@ -79,36 +94,56 @@ entry:
@.str13 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
@.str14 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
-define i32 @PR4641(i32 %argc, i8** %argv) nounwind {
+define i32 @PR4641(i32 %argc, i8** %argv, i1 %c1, i8* %ptr) nounwind {
+; CHECK-LABEL: @PR4641(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: call void @exit(i32 0) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[COND392:%.*]] = select i1 [[C1:%.*]], i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str13, i32 0, i32 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str14, i32 0, i32 0)
+; CHECK-NEXT: [[CALL393:%.*]] = call %struct.__sFILE* @fopen(i8* [[PTR:%.*]], i8* [[COND392]]) #[[ATTR1]]
+; CHECK-NEXT: unreachable
+;
entry:
- call void @exit(i32 0) nounwind
- %cond392 = select i1 undef, i8* getelementptr ([2 x i8], [2 x i8]* @.str13, i32 0, i32 0), i8* getelementptr ([2 x i8], [2 x i8]* @.str14, i32 0, i32 0) ; <i8*> [#uses=1]
- %call393 = call %struct.__sFILE* @fopen(i8* undef, i8* %cond392) nounwind ; <%struct.__sFILE*> [#uses=0]
- unreachable
+ call void @exit(i32 0) nounwind
+ %cond392 = select i1 %c1, i8* getelementptr ([2 x i8], [2 x i8]* @.str13, i32 0, i32 0), i8* getelementptr ([2 x i8], [2 x i8]* @.str14, i32 0, i32 0) ; <i8*> [#uses=1]
+ %call393 = call %struct.__sFILE* @fopen(i8* %ptr, i8* %cond392) nounwind ; <%struct.__sFILE*> [#uses=0]
+ unreachable
}
declare %struct.__sFILE* @fopen(i8*, i8*)
declare void @exit(i32)
-define i32 @PR4645() {
+define i32 @PR4645(i1 %c1) {
+; CHECK-LABEL: @PR4645(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[IF_THEN:%.*]]
+; CHECK: lor.lhs.false:
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[IF_THEN]], label [[FOR_COND:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: call void @exit(i32 1)
+; CHECK-NEXT: br label [[FOR_COND]]
+; CHECK: for.cond:
+; CHECK-NEXT: unreachable
+; CHECK: for.end:
+; CHECK-NEXT: br label [[FOR_COND]]
+;
entry:
- br label %if.then
+ br label %if.then
lor.lhs.false: ; preds = %while.body
- br i1 undef, label %if.then, label %for.cond
+ br i1 %c1, label %if.then, label %for.cond
if.then: ; preds = %lor.lhs.false, %while.body
- call void @exit(i32 1)
- br label %for.cond
+ call void @exit(i32 1)
+ br label %for.cond
for.cond: ; preds = %for.end, %if.then, %lor.lhs.false
- %j.0 = phi i32 [ %inc47, %for.end ], [ 0, %if.then ], [ 0, %lor.lhs.false ] ; <i32> [#uses=1]
- unreachable
+ %j.0 = phi i32 [ %inc47, %for.end ], [ 0, %if.then ], [ 0, %lor.lhs.false ] ; <i32> [#uses=1]
+ unreachable
for.end: ; preds = %for.cond20
- %inc47 = add i32 %j.0, 1 ; <i32> [#uses=1]
- br label %for.cond
+ %inc47 = add i32 %j.0, 1 ; <i32> [#uses=1]
+ br label %for.cond
}
@h = constant [2 x i8] c"h\00" ; <[2 x i8]*> [#uses=1]
@@ -116,6 +151,9 @@ for.end: ; preds = %for.cond20
@hello_u = constant [8 x i8] c"hello_u\00" ; <[8 x i8]*> [#uses=1]
define i32 @MemCpy() {
+; CHECK-LABEL: @MemCpy(
+; CHECK-NEXT: ret i32 0
+;
%h_p = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
%hel_p = getelementptr [4 x i8], [4 x i8]* @hel, i32 0, i32 0
%hello_u_p = getelementptr [8 x i8], [8 x i8]* @hello_u, i32 0, i32 0
@@ -126,9 +164,6 @@ define i32 @MemCpy() {
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %target_p, i8* align 8 %hello_u_p, i32 8, i1 false)
ret i32 0
-; CHECK-LABEL: @MemCpy(
-; CHECK-NOT: llvm.memcpy
-; CHECK: ret i32 0
}
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
@@ -137,7 +172,8 @@ declare i32 @strcmp(i8*, i8*) #0
define void @test9(i8* %x) {
; CHECK-LABEL: @test9(
-; CHECK-NOT: strcmp
+; CHECK-NEXT: ret void
+;
%y = call i32 @strcmp(i8* %x, i8* %x) #1
ret void
}
@@ -151,7 +187,7 @@ declare i32 @toascii(i8)
define i32 @fake_isdigit(i8 %x) {
; CHECK-LABEL: @fake_isdigit(
-; CHECK-NEXT: [[Y:%.*]] = call i32 @isdigit(i8 %x)
+; CHECK-NEXT: [[Y:%.*]] = call i32 @isdigit(i8 [[X:%.*]])
; CHECK-NEXT: ret i32 [[Y]]
;
%y = call i32 @isdigit(i8 %x)
@@ -160,7 +196,7 @@ define i32 @fake_isdigit(i8 %x) {
define i32 @fake_isascii(i8 %x) {
; CHECK-LABEL: @fake_isascii(
-; CHECK-NEXT: [[Y:%.*]] = call i32 @isascii(i8 %x)
+; CHECK-NEXT: [[Y:%.*]] = call i32 @isascii(i8 [[X:%.*]])
; CHECK-NEXT: ret i32 [[Y]]
;
%y = call i32 @isascii(i8 %x)
@@ -169,7 +205,7 @@ define i32 @fake_isascii(i8 %x) {
define i32 @fake_toascii(i8 %x) {
; CHECK-LABEL: @fake_toascii(
-; CHECK-NEXT: [[Y:%.*]] = call i32 @toascii(i8 %x)
+; CHECK-NEXT: [[Y:%.*]] = call i32 @toascii(i8 [[X:%.*]])
; CHECK-NEXT: ret i32 [[Y]]
;
%y = call i32 @toascii(i8 %x)
@@ -182,21 +218,24 @@ declare double @exp2(double)
; check to make sure only the correct libcall attributes are used
define double @fake_exp2(double %x) {
; CHECK-LABEL: @fake_exp2(
-; CHECK-NEXT: [[Y:%.*]] = call double @exp2(double %x)
-; CHECK-NEXT: ret double [[Y]]
+; CHECK-NEXT: [[EXP2:%.*]] = call double @exp2(double [[X:%.*]])
+; CHECK-NEXT: ret double [[EXP2]]
+;
%y = call inreg double @pow(double inreg 2.0, double inreg %x)
ret double %y
}
define double @fake_ldexp(i32 %x) {
; CHECK32-LABEL: @fake_ldexp(
-; CHECK32-NEXT: [[Z:%.*]] = call double @ldexp(double 1.0{{.*}}, i32 %x)
-; CHECK32-NEXT: ret double [[Z]]
-
+; CHECK32-NEXT: [[LDEXP:%.*]] = call double @ldexp(double 1.000000e+00, i32 [[X:%.*]])
+; CHECK32-NEXT: ret double [[LDEXP]]
+;
; CHECK16-LABEL: @fake_ldexp(
-; CHECK16-NEXT: [[Y:%.*]] = sitofp i32 %x to double
+; CHECK16-NEXT: [[Y:%.*]] = sitofp i32 [[X:%.*]] to double
; CHECK16-NEXT: [[Z:%.*]] = call inreg double @exp2(double [[Y]])
; CHECK16-NEXT: ret double [[Z]]
+;
+
%y = sitofp i32 %x to double
%z = call inreg double @exp2(double %y)
@@ -204,13 +243,15 @@ define double @fake_ldexp(i32 %x) {
}
define double @fake_ldexp_16(i16 %x) {
; CHECK32-LABEL: @fake_ldexp_16(
-; CHECK32-NEXT: [[Y:%.*]] = sext i16 %x to i32
-; CHECK32-NEXT: [[Z:%.*]] = call double @ldexp(double 1.0{{.*}}, i32 [[Y]])
-; CHECK32-NEXT: ret double [[Z]]
-
+; CHECK32-NEXT: [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
+; CHECK32-NEXT: [[LDEXP:%.*]] = call double @ldexp(double 1.000000e+00, i32 [[TMP1]])
+; CHECK32-NEXT: ret double [[LDEXP]]
+;
; CHECK16-LABEL: @fake_ldexp_16(
-; CHECK16-NEXT: [[Z:%.*]] = call double @ldexp(double 1.0{{.*}}, i16 %x)
-; CHECK16-NEXT: ret double [[Z]]
+; CHECK16-NEXT: [[LDEXP:%.*]] = call double @ldexp(double 1.000000e+00, i16 [[X:%.*]])
+; CHECK16-NEXT: ret double [[LDEXP]]
+;
+
%y = sitofp i16 %x to double
%z = call inreg double @exp2(double %y)
@@ -221,12 +262,12 @@ define double @fake_ldexp_16(i16 %x) {
declare i32 @snprintf(i8*, double, i32*)
-define i32 @fake_snprintf(i32 %buf, double %len, i32 * %str) {
+define i32 @fake_snprintf(i32 %buf, double %len, i32 * %str, i8* %ptr) {
; CHECK-LABEL: @fake_snprintf(
-; CHECK-NEXT: [[CALL:%.*]] = call i32 @snprintf(i8* undef, double [[LEN:%.*]], i32* [[STR:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = call i32 @snprintf(i8* [[PTR:%.*]], double [[LEN:%.*]], i32* [[STR:%.*]])
; CHECK-NEXT: ret i32 [[CALL]]
;
- %call = call i32 @snprintf(i8* undef, double %len, i32* %str)
+ %call = call i32 @snprintf(i8* %ptr, double %len, i32* %str)
ret i32 %call
}
@@ -248,10 +289,12 @@ define i4 @strlen(i8* %s) {
declare i8* @__stpncpy_chk(i8* noundef, i8* noundef, i32 noundef, i32 noundef)
define signext i32 @emit_stpncpy() {
; CHECK-LABEL: @emit_stpncpy(
-; CHECK-NEXT: call i8* @stpncpy({{.*}} @b, {{.*}} @a, {{.*}} i32 2)
+; CHECK-NEXT: [[STPNCPY:%.*]] = call i8* @stpncpy(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @b, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @a, i32 0, i32 0), i32 2)
+; CHECK-NEXT: ret i32 0
+;
%call = call i8* @__stpncpy_chk(i8* noundef getelementptr inbounds ([5 x i8], [5 x i8]* @b, i32 0, i32 0),
- i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @a, i32 0, i32 0),
- i32 noundef 2, i32 noundef 5)
+ i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @a, i32 0, i32 0),
+ i32 noundef 2, i32 noundef 5)
ret i32 0
}
diff --git a/llvm/test/Transforms/InstCombine/storemerge-dbg.ll b/llvm/test/Transforms/InstCombine/storemerge-dbg.ll
index 52fb3bb5c2491..b952b897719b7 100644
--- a/llvm/test/Transforms/InstCombine/storemerge-dbg.ll
+++ b/llvm/test/Transforms/InstCombine/storemerge-dbg.ll
@@ -3,10 +3,10 @@
declare i32 @escape(i32)
; CHECK-LABEL: define {{.*}}@foo(
-define i32 @foo() {
+define i32 @foo(i1 %c1) {
entry:
%baz = alloca i32
- br i1 undef, label %lhs, label %rhs
+ br i1 %c1, label %lhs, label %rhs
lhs:
store i32 1, i32* %baz
diff --git a/llvm/test/Transforms/InstCombine/type_pun-inseltpoison.ll b/llvm/test/Transforms/InstCombine/type_pun-inseltpoison.ll
index 665844b314944..49b6f3be0a994 100644
--- a/llvm/test/Transforms/InstCombine/type_pun-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/type_pun-inseltpoison.ll
@@ -98,25 +98,25 @@ define { float, i32 } @type_pun_float_i32(<16 x i8> %in) {
; CHECK-NEXT: [[SROA_EXTRACT:%.*]] = extractelement <4 x i32> [[SROA_BC]], i64 0
; CHECK-NEXT: [[SROA_BC1:%.*]] = bitcast <16 x i8> [[IN]] to <4 x float>
; CHECK-NEXT: [[SROA_EXTRACT2:%.*]] = extractelement <4 x float> [[SROA_BC1]], i64 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { float, i32 } undef, float [[SROA_EXTRACT2]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { float, i32 } poison, float [[SROA_EXTRACT2]], 0
; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { float, i32 } [[TMP1]], i32 [[SROA_EXTRACT]], 1
; CHECK-NEXT: ret { float, i32 } [[TMP2]]
;
%sroa = shufflevector <16 x i8> %in, <16 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%f = bitcast <4 x i8> %sroa to float
%i = bitcast <4 x i8> %sroa to i32
- %1 = insertvalue { float, i32 } undef, float %f, 0
+ %1 = insertvalue { float, i32 } poison, float %f, 0
%2 = insertvalue { float, i32 } %1, i32 %i, 1
ret { float, i32 } %2
}
; Type punning two i32 values, with control flow.
; Verify that the bitcast is shared and dominates usage.
-define i32 @type_pun_i32_ctrl(<16 x i8> %in) {
+define i32 @type_pun_i32_ctrl(<16 x i8> %in, i1 %c1) {
; CHECK-LABEL: @type_pun_i32_ctrl(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[SROA_BC:%.*]] = bitcast <16 x i8> [[IN:%.*]] to <4 x i32>
-; CHECK-NEXT: br i1 undef, label [[LEFT:%.*]], label [[RIGHT:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[LEFT:%.*]], label [[RIGHT:%.*]]
; CHECK: left:
; CHECK-NEXT: [[SROA_EXTRACT1:%.*]] = extractelement <4 x i32> [[SROA_BC]], i64 0
; CHECK-NEXT: br label [[TAIL:%.*]]
@@ -129,7 +129,7 @@ define i32 @type_pun_i32_ctrl(<16 x i8> %in) {
;
entry:
%sroa = shufflevector <16 x i8> %in, <16 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- br i1 undef, label %left, label %right
+ br i1 %c1, label %left, label %right
left:
%lhs = bitcast <4 x i8> %sroa to i32
br label %tail
diff --git a/llvm/test/Transforms/InstCombine/type_pun.ll b/llvm/test/Transforms/InstCombine/type_pun.ll
index 6fc878aeae65f..5ca18842af62e 100644
--- a/llvm/test/Transforms/InstCombine/type_pun.ll
+++ b/llvm/test/Transforms/InstCombine/type_pun.ll
@@ -112,11 +112,11 @@ define { float, i32 } @type_pun_float_i32(<16 x i8> %in) {
; Type punning two i32 values, with control flow.
; Verify that the bitcast is shared and dominates usage.
-define i32 @type_pun_i32_ctrl(<16 x i8> %in) {
+define i32 @type_pun_i32_ctrl(<16 x i8> %in, i1 %c1) {
; CHECK-LABEL: @type_pun_i32_ctrl(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[SROA_BC:%.*]] = bitcast <16 x i8> [[IN:%.*]] to <4 x i32>
-; CHECK-NEXT: br i1 undef, label [[LEFT:%.*]], label [[RIGHT:%.*]]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[LEFT:%.*]], label [[RIGHT:%.*]]
; CHECK: left:
; CHECK-NEXT: [[SROA_EXTRACT1:%.*]] = extractelement <4 x i32> [[SROA_BC]], i64 0
; CHECK-NEXT: br label [[TAIL:%.*]]
@@ -129,7 +129,7 @@ define i32 @type_pun_i32_ctrl(<16 x i8> %in) {
;
entry:
%sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- br i1 undef, label %left, label %right
+ br i1 %c1, label %left, label %right
left:
%lhs = bitcast <4 x i8> %sroa to i32
br label %tail
diff --git a/llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
index df990b3c4cd28..99bff990a2c6c 100644
--- a/llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
@@ -125,15 +125,15 @@ ret:
ret void
}
-define i1 @g(<3 x i32> %input_2) {
+define i1 @g(<3 x i32> %input_2, i1 %c1) {
; CHECK-LABEL: @g(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i32> [[INPUT_2:%.*]], i64 0
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP4:%.*]], [[FOR_BODY:%.*]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ undef, [[ENTRY]] ], [ [[TMP3:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: br i1 undef, label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ poison, [[ENTRY]] ], [ [[TMP3:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[FOR_END:%.*]], label [[FOR_BODY]]
; CHECK: for.body:
; CHECK-NEXT: [[TMP3]] = add i32 [[TMP2]], -1
; CHECK-NEXT: [[SUB44_ELT:%.*]] = sub i32 0, [[TMP2]]
@@ -148,8 +148,8 @@ entry:
for.cond:
%input_2.addr.0 = phi <3 x i32> [ %input_2, %entry ], [ %div45, %for.body ]
- %input_1.addr.1 = phi <3 x i32> [ undef, %entry ], [ %dec43, %for.body ]
- br i1 undef, label %for.end, label %for.body
+ %input_1.addr.1 = phi <3 x i32> [ poison, %entry ], [ %dec43, %for.body ]
+ br i1 %c1, label %for.end, label %for.body
for.body:
%dec43 = add <3 x i32> %input_1.addr.1, <i32 -1, i32 -1, i32 -1>
diff --git a/llvm/test/Transforms/InstCombine/vec_phi_extract.ll b/llvm/test/Transforms/InstCombine/vec_phi_extract.ll
index 39b0e3d07b303..035df5b25bf65 100644
--- a/llvm/test/Transforms/InstCombine/vec_phi_extract.ll
+++ b/llvm/test/Transforms/InstCombine/vec_phi_extract.ll
@@ -125,15 +125,15 @@ ret:
ret void
}
-define i1 @g(<3 x i32> %input_2) {
+define i1 @g(<3 x i32> %input_2, i1 %c1) {
; CHECK-LABEL: @g(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i32> [[INPUT_2:%.*]], i64 0
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP4:%.*]], [[FOR_BODY:%.*]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ undef, [[ENTRY]] ], [ [[TMP3:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: br i1 undef, label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ poison, [[ENTRY]] ], [ [[TMP3:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[FOR_END:%.*]], label [[FOR_BODY]]
; CHECK: for.body:
; CHECK-NEXT: [[TMP3]] = add i32 [[TMP2]], -1
; CHECK-NEXT: [[SUB44_ELT:%.*]] = sub i32 0, [[TMP2]]
@@ -148,8 +148,8 @@ entry:
for.cond:
%input_2.addr.0 = phi <3 x i32> [ %input_2, %entry ], [ %div45, %for.body ]
- %input_1.addr.1 = phi <3 x i32> [ undef, %entry ], [ %dec43, %for.body ]
- br i1 undef, label %for.end, label %for.body
+ %input_1.addr.1 = phi <3 x i32> [ poison, %entry ], [ %dec43, %for.body ]
+ br i1 %c1, label %for.end, label %for.body
for.body:
%dec43 = add <3 x i32> %input_1.addr.1, <i32 -1, i32 -1, i32 -1>
diff --git a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
index f03d952993970..5350e8a52d587 100644
--- a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
+++ b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
@@ -217,13 +217,13 @@ define i8 @PR49475_infloop(i32 %t0, i16 %insert, i64 %e, i8 %i162) {
; This would infinite loop because knownbits changed between checking
; if a transform was profitable and actually doing the transform.
-define i1 @PR51762(i32 *%i, i32 %t0, i16 %t1, i64* %p, i32* %d, i32* %f, i32 %p2) {
+define i1 @PR51762(i32 *%i, i32 %t0, i16 %t1, i64* %p, i32* %d, i32* %f, i32 %p2, i1 %c1) {
; CHECK-LABEL: @PR51762(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
-; CHECK-NEXT: [[I_SROA_8_0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[I_SROA_8_0_EXTRACT_TRUNC:%.*]], [[COND_TRUE:%.*]] ]
-; CHECK-NEXT: br i1 undef, label [[COND_TRUE]], label [[FOR_END11:%.*]]
+; CHECK-NEXT: [[I_SROA_8_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[I_SROA_8_0_EXTRACT_TRUNC:%.*]], [[COND_TRUE:%.*]] ]
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[COND_TRUE]], label [[FOR_END11:%.*]]
; CHECK: cond.true:
; CHECK-NEXT: [[I_SROA_8_0_EXTRACT_TRUNC]] = ashr i32 [[T0:%.*]], 31
; CHECK-NEXT: br label [[FOR_COND]]
@@ -257,8 +257,8 @@ entry:
br label %for.cond
for.cond:
- %i.sroa.8.0 = phi i32 [ undef, %entry ], [ %i.sroa.8.0.extract.trunc, %cond.true ]
- br i1 undef, label %cond.true, label %for.end11
+ %i.sroa.8.0 = phi i32 [ poison, %entry ], [ %i.sroa.8.0.extract.trunc, %cond.true ]
+ br i1 %c1, label %cond.true, label %for.end11
cond.true:
%i.sroa.8.0.extract.trunc = ashr i32 %t0, 31
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