[PATCH] D127254: [SelectionDAGISel] Chain any mayRaiseFPException instruction created from a strict FP node

[Ulrich Weigand via Phabricator via llvm-commits]

uweigand added a comment.

>From a SystemZ perspective this looks good to me.



================
Comment at: llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll:4301
+; SZ13-NEXT:    vl %v0, 0(%r1), 3
+; SZ13-NEXT:    vfidb %v24, %v0, 0, 0
 ; SZ13-NEXT:    br %r14
----------------
Not sure why this patch causes the two output registers to be computed in reverse order now, but either order should be fine.  (And now the order in vectorized code matches the order in scalar code ...)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127254/new/

https://reviews.llvm.org/D127254