[PATCH] D127198: [AMDGPU][MC][GFX1013] Enable image_msaa_load

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf8aba9995ad9: [AMDGPU][MC][GFX1013] Enable image_msaa_load (authored by dp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127198/new/

https://reviews.llvm.org/D127198

Files:
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/test/MC/AMDGPU/gfx1013.s


Index: llvm/test/MC/AMDGPU/gfx1013.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AMDGPU/gfx1013.s
@@ -0,0 +1,55 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck %s
+
+image_bvh64_intersect_ray v[5:8], v[1:16], s[8:11]
+// CHECK: [0x01,0x9f,0x9c,0xf1,0x01,0x05,0x02,0x00]
+
+image_bvh64_intersect_ray v[5:8], v[240:255], s[8:11] a16
+// CHECK: [0x01,0x9f,0x9c,0xf1,0xf0,0x05,0x02,0x40]
+
+image_bvh64_intersect_ray v[5:8], v[1:16], ttmp[12:15]
+// CHECK: [0x01,0x9f,0x9c,0xf1,0x01,0x05,0x1e,0x00]
+
+image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40, v42], s[12:15]
+// CHECK: encoding: [0x07,0x9f,0x9c,0xf1,0x32,0x27,0x03,0x00,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x13,0x25,0x28,0x2a,0x00]
+
+image_bvh_intersect_ray v[252:255], v[1:16], s[8:11]
+// CHECK: [0x01,0x9f,0x98,0xf1,0x01,0xfc,0x02,0x00]
+
+image_bvh_intersect_ray v[5:8], v[248:255], s[8:11] a16
+// CHECK: [0x01,0x9f,0x98,0xf1,0xf8,0x05,0x02,0x40]
+
+image_bvh_intersect_ray v[5:8], v[1:16], ttmp[12:15]
+// CHECK: [0x01,0x9f,0x98,0xf1,0x01,0x05,0x1e,0x00]
+
+image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40], s[12:15]
+// CHECK: encoding: [0x07,0x9f,0x98,0xf1,0x32,0x27,0x03,0x00,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x13,0x25,0x28,0x00,0x00]
+
+image_msaa_load v[5:6], v[1:4], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
+// CHECK: [0x39,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_msaa_load v[5:7], v[1:4], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY tfe
+// CHECK: [0x39,0x03,0x01,0xf0,0x01,0x05,0x02,0x00]
+
+image_msaa_load v5, v[1:4], s[8:15] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY d16
+// CHECK: [0x39,0x08,0x00,0xf0,0x01,0x05,0x02,0x80]
+
+image_msaa_load v[5:6], v[1:2], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16
+// CHECK: [0x39,0x03,0x00,0xf0,0x01,0x05,0x02,0x40]
+
+image_msaa_load v[5:6], v[1:3], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA
+// CHECK: [0x31,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_msaa_load v[5:6], v[1:4], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
+// CHECK: [0x39,0x13,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_msaa_load v[5:6], v[1:4], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY glc
+// CHECK: [0x39,0x23,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_msaa_load v[5:6], v[1:4], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY slc
+// CHECK: [0x39,0x03,0x00,0xf2,0x01,0x05,0x02,0x00]
+
+image_msaa_load v[5:6], v[1:4], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY dlc
+// CHECK: [0xb9,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_msaa_load v[5:6], v[1:4], s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY lwe
+// CHECK: [0x39,0x03,0x02,0xf0,0x01,0x05,0x02,0x00]
Index: llvm/lib/Target/AMDGPU/MIMGInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -1361,7 +1361,7 @@
 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", mimgopc<0x7e>>;
 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", mimgopc<0x7f>>;
 
-let SubtargetPredicate = isGFX10Only, OtherPredicates = [HasGFX10_BEncoding] in
+let SubtargetPredicate = isGFX10Only, OtherPredicates = [HasGFX10_AEncoding] in
 defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<MIMG.NOP, 0x80>, "image_msaa_load", 1, 0, 0, 1>;
 
 let OtherPredicates = [HasGFX10_AEncoding] in


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