[PATCH] D127315: [AMDGPU] New GFX11 intrinsic llvm.amdgcn.s.sendmsg.rtn

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll:127
+}
+
+declare i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32)
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foad wrote:
> arsenm wrote:
> > Maybe test some invalid immediates?
> Done, but validity is a slippery concept here. Do you think these should be diagnosed at some stage? I would be tempted to say the intrinsic should at least accept any unsigned 8-bit immediate, which is what the instruction encodes.
> 
> (The next level of verification would be to insist that bit 7 is set, since that distinguishes messages that are expected to return something. And the next level after that would be to only accept the specific message numbers that are currently defined to do something useful.)
We don't have a consistent strategy. Some places use i16 to avoid this issue, others clamp the bits


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https://reviews.llvm.org/D127315