[PATCH] D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM w/minor required change.



================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1432
+    MachineInstr &MI = *I++;
+    uint64_t TSFlags = MI.getDesc().TSFlags;
+    if (isFaultFirstLoad(MI)) {
----------------
TSFlags appears dead, remove it before commit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126794/new/

https://reviews.llvm.org/D126794