[PATCH] D127329: [RISCV] A vector instruction without a tail is always tail agnostic

[Philip Reames via Phabricator via llvm-commits]

reames planned changes to this revision.
reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2520
+
+  // A tail undisturbed (tu) op with no tail is tail agnostic (ta)
+  if (!(Policy & RISCVII::TAIL_AGNOSTIC) && isa<ConstantSDNode>(VL) &&
----------------
craig.topper wrote:
> Just to confirm.
> 
> vcompress doesn't have a policy operand so this wouldn't apply? I ask because vcompress writes less than VL elements and the tail policy applies to the other elements.
> 
> reductions and vmv.s.x also don't have policy operand.
Just noting this question is still open.  I'm going to get dig into each of these cases, but I have not done it yet.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127329/new/

https://reviews.llvm.org/D127329