[PATCH] D127329: [RISCV] A vector instruction without a tail is always tail agnostic

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2491
+
+  const RISCVInstrInfo *TII = static_cast<const RISCVInstrInfo *>(
+      Subtarget->getInstrInfo());
----------------
craig.topper wrote:
> Assuming Subtarget is RISCVSubtarget*, doesn't RISCVSubtarget::getInstrInfo() return RISCVInstrInfo * without a cast?
I'd copied this from somewhere else, and only partially fixed it up.  The source of my copy was fixed in 28be4b745.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2534
+                                        VecPolicy->getValueType(0));
+  SmallVector<SDValue, 8> Ops;
+  for (unsigned I = 0, E = N->getNumOperands(); I != E; I++) {
----------------
craig.topper wrote:
> Why not copy all values using the SmallVector range constructor and overwrite Ops[VecPolicyOpNum] afterwards.
Good idea, will do.


Repository:
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  https://reviews.llvm.org/D127329/new/

https://reviews.llvm.org/D127329