[PATCH] D127344: [AMDGPU] Fix hazard handling of v_cmpx to permlane
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 9 10:34:10 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5c974d086c22: [AMDGPU] Fix hazard handling of v_cmpx to permlane (authored by rampitec).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D127344/new/
https://reviews.llvm.org/D127344
Files:
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
Index: llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
+++ llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
@@ -144,3 +144,26 @@
$vgpr1 = V_PERMLANE16_B32_e64 0, undef $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, undef $vgpr1, 0, implicit $exec
S_ENDPGM 0
...
+
+# GCN-LABEL: name: hazard_vcmpx_e64_permlane16
+# GCN: V_CMPX_LE_F32_nosdst_e64
+# GCN: S_ADD_U32
+# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+# GCN-NEXT: V_PERMLANE16_B32_e64
+---
+name: hazard_vcmpx_e64_permlane16
+body: |
+ bb.0:
+ successors: %bb.1
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+ V_CMPX_LE_F32_nosdst_e64 0, 0, 0, $vgpr0, 0, implicit-def $exec, implicit $mode, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ $vgpr1 = IMPLICIT_DEF
+ $vgpr2 = IMPLICIT_DEF
+ $sgpr0 = IMPLICIT_DEF
+ $sgpr1 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
+ $vgpr1 = V_PERMLANE16_B32_e64 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
+ S_ENDPGM 0
+...
Index: llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
@@ -0,0 +1,24 @@
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
+
+# GCN-LABEL: name: hazard_vcmpx_sdwa_permlane16
+# GCN: V_CMPX_LE_F32_nosdst_sdwa
+# GCN: S_ADD_U32
+# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+# GCN-NEXT: V_PERMLANE16_B32_e64
+---
+name: hazard_vcmpx_sdwa_permlane16
+body: |
+ bb.0:
+ successors: %bb.1
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+ V_CMPX_LE_F32_nosdst_sdwa 0, $vgpr0, 0, $vgpr0, 0, 0, implicit-def $exec, implicit $mode, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ $vgpr1 = IMPLICIT_DEF
+ $vgpr2 = IMPLICIT_DEF
+ $sgpr0 = IMPLICIT_DEF
+ $sgpr1 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
+ $vgpr1 = V_PERMLANE16_B32_e64 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
+ S_ENDPGM 0
+...
Index: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1038,7 +1038,12 @@
return false;
const SIInstrInfo *TII = ST.getInstrInfo();
- auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isVOPC(MI); };
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ auto IsHazardFn = [TII, TRI](const MachineInstr &MI) {
+ return (TII->isVOPC(MI) ||
+ ((TII->isVOP3(MI) || TII->isSDWA(MI)) && MI.isCompare())) &&
+ MI.modifiesRegister(AMDGPU::EXEC, TRI);
+ };
auto IsExpiredFn = [](const MachineInstr &MI, int) {
unsigned Opc = MI.getOpcode();
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