[llvm] 5c974d0 - [AMDGPU] Fix hazard handling of v_cmpx to permlane
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 9 10:34:06 PDT 2022
Author: Stanislav Mekhanoshin
Date: 2022-06-09T10:33:54-07:00
New Revision: 5c974d086c22d519e3e649f1d5fe213b03d6ba25
URL: https://github.com/llvm/llvm-project/commit/5c974d086c22d519e3e649f1d5fe213b03d6ba25
DIFF: https://github.com/llvm/llvm-project/commit/5c974d086c22d519e3e649f1d5fe213b03d6ba25.diff
LOG: [AMDGPU] Fix hazard handling of v_cmpx to permlane
- VOP3 and SDWA forms of V_CMPX were not handled
- Hazard only exists if the compare defines EXEC (i.e. V_CMPX)
forwarded to the permlane.
Differential Revision: https://reviews.llvm.org/D127344
Added:
llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
Modified:
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 51d3704d5645..099f4faf0b89 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1038,7 +1038,12 @@ bool GCNHazardRecognizer::fixVcmpxPermlaneHazards(MachineInstr *MI) {
return false;
const SIInstrInfo *TII = ST.getInstrInfo();
- auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isVOPC(MI); };
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ auto IsHazardFn = [TII, TRI](const MachineInstr &MI) {
+ return (TII->isVOPC(MI) ||
+ ((TII->isVOP3(MI) || TII->isSDWA(MI)) && MI.isCompare())) &&
+ MI.modifiesRegister(AMDGPU::EXEC, TRI);
+ };
auto IsExpiredFn = [](const MachineInstr &MI, int) {
unsigned Opc = MI.getOpcode();
diff --git a/llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir b/llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
new file mode 100644
index 000000000000..197232da66a4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
@@ -0,0 +1,24 @@
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
+
+# GCN-LABEL: name: hazard_vcmpx_sdwa_permlane16
+# GCN: V_CMPX_LE_F32_nosdst_sdwa
+# GCN: S_ADD_U32
+# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+# GCN-NEXT: V_PERMLANE16_B32_e64
+---
+name: hazard_vcmpx_sdwa_permlane16
+body: |
+ bb.0:
+ successors: %bb.1
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+ V_CMPX_LE_F32_nosdst_sdwa 0, $vgpr0, 0, $vgpr0, 0, 0, implicit-def $exec, implicit $mode, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ $vgpr1 = IMPLICIT_DEF
+ $vgpr2 = IMPLICIT_DEF
+ $sgpr0 = IMPLICIT_DEF
+ $sgpr1 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
+ $vgpr1 = V_PERMLANE16_B32_e64 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir b/llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
index b11c507f5580..534a9c1c01ca 100644
--- a/llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
@@ -144,3 +144,26 @@ body: |
$vgpr1 = V_PERMLANE16_B32_e64 0, undef $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, undef $vgpr1, 0, implicit $exec
S_ENDPGM 0
...
+
+# GCN-LABEL: name: hazard_vcmpx_e64_permlane16
+# GCN: V_CMPX_LE_F32_nosdst_e64
+# GCN: S_ADD_U32
+# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+# GCN-NEXT: V_PERMLANE16_B32_e64
+---
+name: hazard_vcmpx_e64_permlane16
+body: |
+ bb.0:
+ successors: %bb.1
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+ V_CMPX_LE_F32_nosdst_e64 0, 0, 0, $vgpr0, 0, implicit-def $exec, implicit $mode, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ $vgpr1 = IMPLICIT_DEF
+ $vgpr2 = IMPLICIT_DEF
+ $sgpr0 = IMPLICIT_DEF
+ $sgpr1 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
+ $vgpr1 = V_PERMLANE16_B32_e64 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
+ S_ENDPGM 0
+...
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