[PATCH] D127241: [AMDGPU] gfx11 add bits to COMPUTE_PGM_RSRC3

[Konstantin Zhuravlyov via Phabricator via llvm-commits]

kzhuravl added a comment.

In D127241#3570194 <https://reviews.llvm.org/D127241#3570194>, @kzhuravl wrote:

> In D127241#3564469 <https://reviews.llvm.org/D127241#3564469>, @Joe_Nash wrote:
>
>> In D127241#3564460 <https://reviews.llvm.org/D127241#3564460>, @rampitec wrote:
>>
>>> This looks like it affects gfx10 as well, while probably should not?
>>
>> @kzhuravl Do you know about this?
>
> GFX10 is only using COMPUTE_PGM_RSRC3_GFX10_PLUS.SHARED_VGPR_COUNT, the rest of the bits for GFX10 are reserved and must be 0.
>
> GFX11 is using COMPUTE_PGM_RSRC3_GFX10_PLUS.INST_PREF_SIZE and others.
>
> This is similar to how we do other compute program resource registers. E.g.:
>
>   ...
>     COMPUTE_PGM_RSRC1(BULKY, 24, 1),
>     COMPUTE_PGM_RSRC1(CDBG_USER, 25, 1),
>     COMPUTE_PGM_RSRC1(FP16_OVFL, 26, 1),    // GFX9+
>     COMPUTE_PGM_RSRC1(RESERVED0, 27, 2),
>     COMPUTE_PGM_RSRC1(WGP_MODE, 29, 1),     // GFX10+
>     COMPUTE_PGM_RSRC1(MEM_ORDERED, 30, 1),  // GFX10+
>     COMPUTE_PGM_RSRC1(FWD_PROGRESS, 31, 1), // GFX10+
>   ...
>
> The reason we have 2 different compute program resource register 3 is because GFX90A and GFX10 have completely different layout for those. So I think this header file should be fine.
>
> Can you add documentation to AMDGPUUsage in this patch as well?
>
> Thanks

Once assembler support gets added for this, we will have to make sure directives for GFX11 only fields do not work on other generations.


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