[PATCH] D127115: [RFC][DAGCombine] Make sure combined nodes are added back to the worklist in topological order.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll:166
+; RV32-NEXT:    vxor.vv v8, v8, v10, v0.t
+; RV32-NEXT:    ret
+;
----------------
deadalnix wrote:
> It improved numerous tests, but not this one test case.
> 
> Other test cases in this file were improved, so this is going in the right direction.
Interesting, thanks. So previously I was using a case from `fixed-vectors-int.ll` (`sub`) as I assumed it was the same issue as here - it certainly looked very similar. Come to think of it, maybe that was just for i64 vectors as the scalar is illegal on RV32 so generate SPLAT_VECTOR. I'll see if I can dig in to see what's going on here.


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  https://reviews.llvm.org/D127115/new/

https://reviews.llvm.org/D127115