[llvm] 226c564 - [InstCombine] Add vector tests for shl+lshr+and transforms; NFC
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 8 20:14:38 PDT 2022
Author: chenglin.bi
Date: 2022-06-09T11:14:26+08:00
New Revision: 226c564329e2340e2d8a532f9e280691caf279f0
URL: https://github.com/llvm/llvm-project/commit/226c564329e2340e2d8a532f9e280691caf279f0
DIFF: https://github.com/llvm/llvm-project/commit/226c564329e2340e2d8a532f9e280691caf279f0.diff
LOG: [InstCombine] Add vector tests for shl+lshr+and transforms; NFC
D126617
Added:
Modified:
llvm/test/Transforms/InstCombine/and.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 87a469b7c722e..4edd7348ce8ae 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -1622,6 +1622,8 @@ define i8 @not_lshr_bitwidth_mask(i8 %x, i8 %y) {
ret i8 %r
}
+; CTTZ(ShlC) < LShrC
+
define i16 @shl_lshr_pow2_const_case1(i16 %x) {
; CHECK-LABEL: @shl_lshr_pow2_const_case1(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 4, [[X:%.*]]
@@ -1635,6 +1637,123 @@ define i16 @shl_lshr_pow2_const_case1(i16 %x) {
ret i16 %r
}
+define <3 x i16> @shl_lshr_pow2_const_case1_uniform_vec(<3 x i16> %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case1_uniform_vec(
+; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i16> <i16 4, i16 4, i16 4>, [[X:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr <3 x i16> [[SHL]], <i16 6, i16 6, i16 6>
+; CHECK-NEXT: [[R:%.*]] = and <3 x i16> [[LSHR]], <i16 8, i16 8, i16 8>
+; CHECK-NEXT: ret <3 x i16> [[R]]
+;
+ %shl = shl <3 x i16> <i16 4, i16 4, i16 4>, %x
+ %lshr = lshr <3 x i16> %shl, <i16 6, i16 6, i16 6>
+ %r = and <3 x i16> %lshr, <i16 8, i16 8, i16 8>
+ ret <3 x i16> %r
+}
+
+define <3 x i16> @shl_lshr_pow2_const_case1_non_uniform_vec(<3 x i16> %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case1_non_uniform_vec(
+; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i16> <i16 16, i16 8, i16 4>, [[X:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr <3 x i16> [[SHL]], <i16 5, i16 4, i16 3>
+; CHECK-NEXT: [[R:%.*]] = and <3 x i16> [[LSHR]], <i16 8, i16 16, i16 4>
+; CHECK-NEXT: ret <3 x i16> [[R]]
+;
+ %shl = shl <3 x i16> <i16 16, i16 8, i16 4>, %x
+ %lshr = lshr <3 x i16> %shl, <i16 5, i16 4, i16 3>
+ %r = and <3 x i16> %lshr, <i16 8, i16 16, i16 4>
+ ret <3 x i16> %r
+}
+
+define <3 x i16> @shl_lshr_pow2_const_case1_undef1_vec(<3 x i16> %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case1_undef1_vec(
+; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i16> <i16 undef, i16 16, i16 16>, [[X:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr <3 x i16> [[SHL]], <i16 5, i16 5, i16 5>
+; CHECK-NEXT: [[R:%.*]] = and <3 x i16> [[LSHR]], <i16 8, i16 8, i16 8>
+; CHECK-NEXT: ret <3 x i16> [[R]]
+;
+ %shl = shl <3 x i16> <i16 undef, i16 16, i16 16>, %x
+ %lshr = lshr <3 x i16> %shl, <i16 5, i16 5, i16 5>
+ %r = and <3 x i16> %lshr, <i16 8, i16 8, i16 8>
+ ret <3 x i16> %r
+}
+
+define <3 x i16> @shl_lshr_pow2_const_case1_undef2_vec(<3 x i16> %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case1_undef2_vec(
+; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i16> <i16 16, i16 16, i16 16>, [[X:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr <3 x i16> [[SHL]], <i16 undef, i16 5, i16 5>
+; CHECK-NEXT: [[R:%.*]] = and <3 x i16> [[LSHR]], <i16 8, i16 8, i16 8>
+; CHECK-NEXT: ret <3 x i16> [[R]]
+;
+ %shl = shl <3 x i16> <i16 16, i16 16, i16 16>, %x
+ %lshr = lshr <3 x i16> %shl, <i16 undef, i16 5, i16 5>
+ %r = and <3 x i16> %lshr, <i16 8, i16 8, i16 8>
+ ret <3 x i16> %r
+}
+
+define <3 x i16> @shl_lshr_pow2_const_case1_undef3_vec(<3 x i16> %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case1_undef3_vec(
+; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i16> <i16 16, i16 16, i16 16>, [[X:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr <3 x i16> [[SHL]], <i16 5, i16 5, i16 5>
+; CHECK-NEXT: [[R:%.*]] = and <3 x i16> [[LSHR]], <i16 undef, i16 8, i16 8>
+; CHECK-NEXT: ret <3 x i16> [[R]]
+;
+ %shl = shl <3 x i16> <i16 16, i16 16, i16 16>, %x
+ %lshr = lshr <3 x i16> %shl, <i16 5, i16 5, i16 5>
+ %r = and <3 x i16> %lshr, <i16 undef, i16 8, i16 8>
+ ret <3 x i16> %r
+}
+
+; LShrC < CTTZ(ShlC) < LShrC + CTTZ(AndC)
+
+define i16 @shl_lshr_pow2_const_case2(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_case2(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i16 2, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], 8
+; CHECK-NEXT: ret i16 [[R]]
+;
+ %shl = shl i16 16, %x
+ %lshr = lshr i16 %shl, 3
+ %r = and i16 %lshr, 8
+ ret i16 %r
+}
+
+define i16 @shl_lshr_pow2_not_const_case2(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_not_const_case2(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i16 2, [[X:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[TMP1]], 8
+; CHECK-NEXT: [[R:%.*]] = xor i16 [[AND]], 8
+; CHECK-NEXT: ret i16 [[R]]
+;
+ %shl = shl i16 16, %x
+ %lshr = lshr i16 %shl, 3
+ %and = and i16 %lshr, 8
+ %r = xor i16 %and, 8
+ ret i16 %r
+}
+
+; CTTZ(ShlC) > LShrC + CTTZ(AndC)
+
+define i16 @shl_lshr_pow2_const_negative_overflow1(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_negative_overflow1(
+; CHECK-NEXT: ret i16 0
+;
+ %shl = shl i16 4096, %x
+ %lshr = lshr i16 %shl, 6
+ %r = and i16 %lshr, 8
+ ret i16 %r
+}
+
+; LShrC + CTTZ(AndC) > BitWidth
+
+define i16 @shl_lshr_pow2_const_negative_overflow2(i16 %x) {
+; CHECK-LABEL: @shl_lshr_pow2_const_negative_overflow2(
+; CHECK-NEXT: ret i16 0
+;
+ %shl = shl i16 8, %x
+ %lshr = lshr i16 %shl, 6
+ %r = and i16 %lshr, 32768
+ ret i16 %r
+}
+
define i16 @shl_lshr_pow2_const_negative_oneuse(i16 %x) {
; CHECK-LABEL: @shl_lshr_pow2_const_negative_oneuse(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 4, [[X:%.*]]
@@ -1650,7 +1769,6 @@ define i16 @shl_lshr_pow2_const_negative_oneuse(i16 %x) {
ret i16 %r
}
-
define i16 @shl_lshr_pow2_const_negative_nopow2_1(i16 %x) {
; CHECK-LABEL: @shl_lshr_pow2_const_negative_nopow2_1(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 3, [[X:%.*]]
@@ -1677,26 +1795,6 @@ define i16 @shl_lshr_pow2_const_negative_nopow2_2(i16 %x) {
ret i16 %r
}
-define i16 @shl_lshr_pow2_const_negative_overflow1(i16 %x) {
-; CHECK-LABEL: @shl_lshr_pow2_const_negative_overflow1(
-; CHECK-NEXT: ret i16 0
-;
- %shl = shl i16 4096, %x
- %lshr = lshr i16 %shl, 6
- %r = and i16 %lshr, 8
- ret i16 %r
-}
-
-define i16 @shl_lshr_pow2_const_negative_overflow2(i16 %x) {
-; CHECK-LABEL: @shl_lshr_pow2_const_negative_overflow2(
-; CHECK-NEXT: ret i16 0
-;
- %shl = shl i16 8, %x
- %lshr = lshr i16 %shl, 6
- %r = and i16 %lshr, 32768
- ret i16 %r
-}
-
define i16 @lshr_lshr_pow2_const(i16 %x) {
; CHECK-LABEL: @lshr_lshr_pow2_const(
; CHECK-NEXT: [[LSHR2:%.*]] = lshr i16 32, [[X:%.*]]
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