[PATCH] D127376: [RISCV] Teach RISCVMergeBaseOffset about cases where we use SHXADD to add some immediates.

[Craig Topper via Phabricator via llvm-commits]

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For an addition with simm14 and simm15 immediates with 2 or 3 trailing bits,
we can use a shXadd instruction and an addi to do the addition.

This patch teaches RISCVMergeBaseOffset to see through this pattern.
I don't think the sh1add case occurs because we use two addis for that,
but I implemented it for completeness.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127376

Files:
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
  llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

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