[PATCH] D127322: [SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST.

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM

> This is certainly at odds with how we handle the other "unpacked" types but I don't think we've ever really agreed how `<vscale x 1 x` should be represented at the register level.

In memory, ``<vscale x 1 x` is tightly packed.  There are no legal `<vscale x 1 x` types on AArch64, so target-independent legalization will eliminate them.

So the question you're asking is really how `<vscale x 1 x` are passed across functions, and in SelectionDAG, across basic blocks.  That's entirely determined by getCopyFromPartsVector()/getCopyToPartsVector() in SelectionDAGBuilder, I think.  I'm fine with the current state, but if you want to mess with it, we can, I guess.  I don't think it directly interacts with anything else.


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https://reviews.llvm.org/D127322