[llvm] 4bcfc41 - [SelectionDAG] Teach computeKnownBits that a nsw self multiply produce a positive value.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-06-08T14:55:58-07:00
New Revision: 4bcfc418464b0bd0169ace715043789cccb77365

URL: https://github.com/llvm/llvm-project/commit/4bcfc418464b0bd0169ace715043789cccb77365
DIFF: https://github.com/llvm/llvm-project/commit/4bcfc418464b0bd0169ace715043789cccb77365.diff

LOG: [SelectionDAG] Teach computeKnownBits that a nsw self multiply produce a positive value.

This matches what we do in IR. For the RISC-V test case, this allows
us to use -8 for the AND mask instead of materializing a constant in a register.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D127335

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
    llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 87c64f7af10b6..a917bf73424a2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3173,6 +3173,14 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
       SelfMultiply &= isGuaranteedNotToBeUndefOrPoison(
           Op.getOperand(0), DemandedElts, false, Depth + 1);
     Known = KnownBits::mul(Known, Known2, SelfMultiply);
+
+    // If the multiplication is known not to overflow, the product of a number
+    // with itself is non-negative. Only do this if we didn't already computed
+    // the opposite value for the sign bit.
+    if (Op->getFlags().hasNoSignedWrap() &&
+        Op.getOperand(0) == Op.getOperand(1) &&
+        !Known.isNegative())
+      Known.makeNonNegative();
     break;
   }
   case ISD::MULHU: {

diff  --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
index 373325fcdfdc1..5bcadf4dce009 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
@@ -24,3 +24,16 @@ define i32 @foo(i32 %x, i32 %y, i32 %z) {
   %g = shl i32 %f, %y
   ret i32 %g
 }
+
+; The sign bit of an nsw self multiply is 0. Make sure we can use this to
+; convert the AND constant to -8.
+define i64 @mul_self_nsw_sign(i64 %x) {
+; CHECK-LABEL: mul_self_nsw_sign:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mul a0, a0, a0
+; CHECK-NEXT:    andi a0, a0, -8
+; CHECK-NEXT:    ret
+  %a = mul nsw i64 %x, %x
+  %b = and i64 %a, 9223372036854775800
+  ret i64 %b
+}

diff  --git a/llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll b/llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll
index 926a177671413..a1b5e6f2ec897 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll
@@ -486,10 +486,10 @@ define i32 @scalar(i16 %a) {
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    smulbb r1, r0, r0
 ; CHECK-NEXT:    movs r0, #127
-; CHECK-NEXT:    asrs r2, r1, #7
+; CHECK-NEXT:    lsrs r2, r1, #7
 ; CHECK-NEXT:    cmp r2, #127
 ; CHECK-NEXT:    it lt
-; CHECK-NEXT:    asrlt r0, r1, #7
+; CHECK-NEXT:    lsrlt r0, r1, #7
 ; CHECK-NEXT:    bx lr
   %e = sext i16 %a to i32
   %d = mul nsw i32 %e, %e