[PATCH] D127329: [RISCV] A vector instruction without a tail is always tail agnostic

[Philip Reames via Phabricator via llvm-commits]

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This change implements a ISEL peephole to replace the tail policy of a vector operation with no tail elements (because AVL is VLMAX) with tail agnostic.  I believe this to be profitable (or at least neutral) on all reasonable hardware.

This could be reasonable done in a couple of different places.  I considered doing this inside RISCVInsertVSETVLI.cpp since the true motivation is - once combined with another change - to eventually get rid of some vsetvli transitions, but this felt more like an instruction selection change.

A couple things for reviewers:

- This is deliberately extremely generic.  The offset code is modeled off what we do in RISCVInsertVSETVLI.cpp, but if there are special cases in SelectionDAG I don't know about, there might be a bug here.
- I'm planning to extend this with a couple other transforms in the nearish future.  The first is going to use VLMAX for AVL immediates we can prove to exceed VLMAX.  The second is going to apply the same policy tweak for unmasked and mask ignoring instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127329

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll

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