[PATCH] D126843: [RISCV] Support (addi (addi globaladdr, C1), C2) in RISCVMergeBaseOffset.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp:208-214
     int64_t Offset = Tail.getOperand(2).getImm();
+
+    // We might have two ADDIs in a row.
+    Register TailDestReg = Tail.getOperand(0).getReg();
+    if (MRI->hasOneUse(TailDestReg)) {
+      MachineInstr &TailTail = *MRI->use_instr_begin(TailDestReg);
+      if (TailTail.getOpcode() == RISCV::ADDI) {
----------------
luismarques wrote:
> BTW, shouldn't the preexisting code check the type of the tail ADDI immediate machine operand (that it is MO_Immediate or something like that)? If so, then the same applies to this second ADDI.
I think it has to be an immediate because we started from a global address LUI+ADDI pair. Any user of that could only be an ADDI with a real immediate. It couldn't be part of another global address and it couldn't be a frame index.


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  https://reviews.llvm.org/D126843/new/

https://reviews.llvm.org/D126843