[PATCH] D127309: [PowerPC] emit VSX instructions instead of VMX instructions for vector loads and stores

[Quinn Pham via Phabricator via llvm-commits]

quinnp created this revision.
Herald added subscribers: steven.zhang, shchenz, kbarton, hiraditya, nemanjai.
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quinnp requested review of this revision.
Herald added a project: LLVM.
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This patch changes the PowerPC backend to generate VSX load/store instructions
for vector loads/stores instead of VMX load/store instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127309

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
  llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
  llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
  llvm/test/CodeGen/PowerPC/crypto_bifs_be.ll
  llvm/test/CodeGen/PowerPC/extract-and-store.ll
  llvm/test/CodeGen/PowerPC/f128-aggregates.ll
  llvm/test/CodeGen/PowerPC/f128-arith.ll
  llvm/test/CodeGen/PowerPC/f128-compare.ll
  llvm/test/CodeGen/PowerPC/f128-conv.ll
  llvm/test/CodeGen/PowerPC/f128-fma.ll
  llvm/test/CodeGen/PowerPC/f128-passByValue.ll
  llvm/test/CodeGen/PowerPC/f128-rounding.ll
  llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
  llvm/test/CodeGen/PowerPC/float-logic-ops.ll
  llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
  llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
  llvm/test/CodeGen/PowerPC/load-and-splat.ll
  llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
  llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
  llvm/test/CodeGen/PowerPC/pcrel_ldst.ll
  llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
  llvm/test/CodeGen/PowerPC/pr25080.ll
  llvm/test/CodeGen/PowerPC/recipest.ll
  llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll
  llvm/test/CodeGen/PowerPC/sat-add.ll
  llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
  llvm/test/CodeGen/PowerPC/signbit-shift.ll
  llvm/test/CodeGen/PowerPC/store_fptoi.ll
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/toc-float.ll
  llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/PowerPC/vavg.ll
  llvm/test/CodeGen/PowerPC/vec-icmpeq-v2i64-p7.ll
  llvm/test/CodeGen/PowerPC/vec-itofp.ll
  llvm/test/CodeGen/PowerPC/vec-trunc.ll
  llvm/test/CodeGen/PowerPC/vec-trunc2.ll
  llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
  llvm/test/CodeGen/PowerPC/vec_constants.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll
  llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
  llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/PowerPC/vector-ldst.ll
  llvm/test/CodeGen/PowerPC/vector-rotates.ll
  llvm/test/CodeGen/PowerPC/vselect-constants.ll
  llvm/test/CodeGen/PowerPC/vsx-ldst.ll
  llvm/test/CodeGen/PowerPC/vsx.ll

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