[PATCH] D125094: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records

[Lucas Prates via Phabricator via llvm-commits]

pratlucas marked an inline comment as done.
pratlucas added inline comments.


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Comment at: llvm/test/CodeGen/Thumb/frame-access.ll:335
+; CHECK-FP-AAPCS: mov r1, r11
+; CHECK-FP-AAPCS: ldr r0, [r0, r1]
+; CHECK: bl i
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efriedma wrote:
> This sequence requires, in general, scavenging two registers.  I'm not sure we can do that in general?  I think we normally only have one emergency spill slot.
> 
> Maybe we can save a register using add instead of mov; something like `ldr r0, .LCPI0_0; add r0, r11; ldr r0, [r0]`.
That's true. Loads aren't affected as they reuse the destination register, but stores would indeed require the scaveging of two registers.
I've updaded the code to use the `add` approach instead.


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https://reviews.llvm.org/D125094