[PATCH] D127210: [AArch64][SME] Add load/store intrinsics

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added a comment.

I'm not going to comment on the design / implementation since I wrote much of it, but I've left a few minor comments



================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp:343-373
+    markSuperRegs(Reserved, AArch64::ZAB0);
+    markSuperRegs(Reserved, AArch64::ZAH0);
+    markSuperRegs(Reserved, AArch64::ZAH1);
+    markSuperRegs(Reserved, AArch64::ZAS0);
+    markSuperRegs(Reserved, AArch64::ZAS1);
+    markSuperRegs(Reserved, AArch64::ZAS2);
+    markSuperRegs(Reserved, AArch64::ZAS3);
----------------
how about:

```  for (MCSubRegIterator SubReg(AArch64::ZA, this, /*self=*/true);
       SubReg.isValid(); ++SubReg)
    Reserved.set(*SubReg);```


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:335
+
+defm : sme_mem_ld_ss_patterns<!cast<Instruction>(NAME # _PSEUDO_B),
+                                !if(is_col, int_aarch64_sme_ld1b_vert,
----------------
nit: indent


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:417
+  let AddedComplexity = 1 in {
+    def : Pat<(Store PPR3bAny:$pg, (addr GPR64sp:$base, GPR64:$offset),                     (imm2tile untyped:$tile), MatrixIndexGPR32Op12_15:$idx),
+              (Inst $tile, $idx, 0, $pg, $base, $offset)>;
----------------
nit: fix formatting


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:476
+
+defm : sme_mem_st_ss_patterns<!cast<Instruction>(NAME # _B),
+                                !if(is_col, int_aarch64_sme_st1b_vert,
----------------
nit: indent


Repository:
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https://reviews.llvm.org/D127210