[llvm] e14d049 - [SplitKit] Handle early clobber + tied to def correctly
Kito Cheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 7 20:33:10 PDT 2022
Author: Kito Cheng
Date: 2022-06-08T11:33:05+08:00
New Revision: e14d04909df4e52e531f6c2e045c3cf9638dd817
URL: https://github.com/llvm/llvm-project/commit/e14d04909df4e52e531f6c2e045c3cf9638dd817
DIFF: https://github.com/llvm/llvm-project/commit/e14d04909df4e52e531f6c2e045c3cf9638dd817.diff
LOG: [SplitKit] Handle early clobber + tied to def correctly
Spliter will try to extend a live range into `r` slot for a use operand,
that's works on most situaion, however that not work correctly when the operand
has tied to def, and the def operand is early clobber.
Give an example to demo what's wrong:
0 %0 = ...
16 early-clobber %0 = Op %0 (tied-def 0), ...
32 ... = Op %0
Before extend:
%0 = [0r, 0d) [16e, 32d)
The point we want to extend is 0d to 16e not 16r in this case, but if
we use 16r here we will extend nothing because that already contained
in [16e, 32d).
This patch add check for detect such case and adjust the extend point.
Detailed explanation for testcase: https://reviews.llvm.org/D126047
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D126048
Added:
Modified:
llvm/lib/CodeGen/SplitKit.cpp
llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index f270c3a648b3e..140a91ae342b2 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -1352,13 +1352,34 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
continue;
// We may want to extend a live range for a partial redef, or for a use
// tied to an early clobber.
- Idx = Idx.getPrevSlot();
- if (!Edit->getParent().liveAt(Idx))
+ if (!Edit->getParent().liveAt(Idx.getPrevSlot()))
continue;
- } else
- Idx = Idx.getRegSlot(true);
+ } else {
+ assert(MO.isUse());
+ bool IsEarlyClobber = false;
+ if (MO.isTied()) {
+ // We want to extend a live range into `e` slot rather than `r` slot if
+ // tied-def is early clobber, because the `e` slot already contained
+ // in the live range of early-clobber tied-def operand, give an example
+ // here:
+ // 0 %0 = ...
+ // 16 early-clobber %0 = Op %0 (tied-def 0), ...
+ // 32 ... = Op %0
+ // Before extend:
+ // %0 = [0r, 0d) [16e, 32d)
+ // The point we want to extend is 0d to 16e not 16r in this case, but if
+ // we use 16r here we will extend nothing because that already contained
+ // in [16e, 32d).
+ unsigned OpIdx = MI->getOperandNo(&MO);
+ unsigned DefOpIdx = MI->findTiedOperandIdx(OpIdx);
+ const MachineOperand &DefOp = MI->getOperand(DefOpIdx);
+ IsEarlyClobber = DefOp.isEarlyClobber();
+ }
+
+ Idx = Idx.getRegSlot(IsEarlyClobber);
+ }
- SlotIndex Next = Idx.getNextSlot();
+ SlotIndex Next = Idx;
if (LI.hasSubRanges()) {
// We have to delay extending subranges until we have seen all operands
// defining the register. This is because a <def,read-undef> operand
diff --git a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
index 33e07b70929a0..ba5b0e1821a40 100644
--- a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
+++ b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
@@ -55,14 +55,14 @@ define void @_Z3foov() {
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vl2r.v v8, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vl2r.v v10, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vl2r.v v12, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vl2r.v v14, (a1) # Unknown-size Folded Reload
-; CHECK-NEXT: vle16.v v14, (a0)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: vl2r.v v16, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, mu
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_40)
; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_40)
@@ -76,11 +76,11 @@ define void @_Z3foov() {
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vsext.vf2 v8, v16, v0.t
+; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vsext.vf2 v10, v8, v0.t
; CHECK-NEXT: lui a0, %hi(var_47)
; CHECK-NEXT: addi a0, a0, %lo(var_47)
-; CHECK-NEXT: vsseg4e16.v v8, (a0)
+; CHECK-NEXT: vsseg4e16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 10
; CHECK-NEXT: mul a0, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir
index a3dfd8c15aa5c..d8a43bd03570a 100644
--- a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir
+++ b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir
@@ -216,7 +216,7 @@ body: |
; CHECK-NEXT: rewr %bb.0 464B:0 early-clobber %28.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %28.sub_vrm2_0:vrn4m2nov0(tied-def 0), %5:vr, $v0, 2, 4, 0, implicit $vl, implicit $vtype
; CHECK-NEXT: rewr %bb.0 512B:0 PseudoVSSEG4E16_V_M2 %28:vrn4m2nov0, %27:gpr, 2, 4, implicit $vl, implicit $vtype
; CHECK-NEXT: rewr %bb.0 216B:1 undef %28.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0 = COPY %29.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0
- ; CHECK-NEXT: queuing new interval: %28 [216r,288r:0)[288r,464e:1)[464e,512r:2) 0 at 216r 1 at 288r 2 at 464e L000000000000000C [216r,216d:0)[464e,512r:1) 0 at 216r 1 at 464e L0000000000000300 [288r,512r:0) 0 at 288r L00000000000000C0 [216r,512r:0) 0 at 216r L0000000000000030 [216r,512r:0) 0 at 216r weight:8.706897e-03
+ ; CHECK-NEXT: queuing new interval: %28 [216r,288r:0)[288r,464e:1)[464e,512r:2) 0 at 216r 1 at 288r 2 at 464e L000000000000000C [216r,464e:0)[464e,512r:1) 0 at 216r 1 at 464e L0000000000000300 [288r,512r:0) 0 at 288r L00000000000000C0 [216r,512r:0) 0 at 216r L0000000000000030 [216r,512r:0) 0 at 216r weight:8.706897e-03
%26:gpr = LUI target-flags(riscv-hi) @var_47
%27:gpr = ADDI %26, target-flags(riscv-lo) @var_47
PseudoVSSEG4E16_V_M2 %25, %27, 2, 4 /* e16 */, implicit $vl, implicit $vtype
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