[PATCH] D126047: [RISCV] Testcase to show wrong register allocation result of subreg liveness

[Kito Cheng via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcbe22c794348: [RISCV] Testcase to show wrong register allocation result of subreg liveness (authored by kito-cheng).

Changed prior to commit:
  https://reviews.llvm.org/D126047?vs=430899&id=435039#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126047/new/

https://reviews.llvm.org/D126047

Files:
  llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
  llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D126047.435039.patch
Type: text/x-patch
Size: 24851 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220608/efac5df9/attachment-0001.bin>