[PATCH] D126617: [InstCombine] Optimize shl+lshr+and conversion pattern

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 updated this revision to Diff 435028.
bcl5980 edited the summary of this revision.
bcl5980 added a comment.

1. Use m_Power2 to match C1 <https://reviews.llvm.org/C1>
2. Remove condition Log2(C1 <https://reviews.llvm.org/C1>) < Log2(C3)+C2
3. Add one more test case when C2 <  Log2(C1 <https://reviews.llvm.org/C1>) < Log2(C3)+C2


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126617/new/

https://reviews.llvm.org/D126617

Files:
  llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
  llvm/test/Transforms/InstCombine/and.ll
  llvm/test/Transforms/InstCombine/icmp-and-shift.ll

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