[PATCH] D127118: [AArch64] Autogenerate sve-fixed-length tests. NFC

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Have you had chance to see if the extra NO_SVE lines can be removed.  I really don't want these tests to require updates when SVE is not being used, whilst at the same time validating no SVE is used, which is what the current single `NO_SVE-NOT` lines verifies.



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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll:4
 ; RUN: llc -aarch64-sve-vector-bits-min=256  < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_256
 ; RUN: llc -aarch64-sve-vector-bits-min=384  < %s | FileCheck %s -check-prefixes=CHECK
 ; RUN: llc -aarch64-sve-vector-bits-min=512  < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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RKSimon wrote:
> Please can you -check-prefixes=CHECK,VBITS_GE_384 to the tests?
Sorry I didn't get to respond before you made the change but I don't think `VBITS_GE_384` makes sense for some (if not all) of the tests you're changing.  The fixed length support it limited to power-of-two values (regardless of the actual target vector length) and so the likely real fix is for the RUN lines where only `aarch64-sve-vector-bits-min` is set to use `VBITS_GE_256`.  You can see this when looking at the output with VBITS_EQ_256 and VBITS_GE_384 being identical.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127118/new/

https://reviews.llvm.org/D127118