[PATCH] D126617: [InstCombine] Optimize shl+lshr+and conversion pattern

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp:1895
+              m_OneUse(m_LShr(m_Shl(m_APInt(C1), m_Value(X)), m_APInt(C2)))) &&
+        C1->isPowerOf2()) {
+      unsigned Log2C1 = C1->countTrailingZeros();
----------------
Use `m_Power2(C1)` ?


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Comment at: llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp:1899
+      unsigned LShrEqBits = Log2C + C2->getZExtValue();
+      if (LShrEqBits < Width && LShrEqBits >= Log2C1) {
+        // iff C,C1 is pow2 and cttz(C1) < cttz(C)+C2 < BitWidth:
----------------
Do we really need both conditions? I removed one assumption, and it still shows as correct:
https://alive2.llvm.org/ce/z/nUAXL9


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126617/new/

https://reviews.llvm.org/D126617