[PATCH] D126989: [AMDGPU] gfx11 VOPC instructions

[Joe Nash via Phabricator via llvm-commits]

Joe_Nash added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir:22
   ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
-  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
+  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 0, [[REG_SEQUENCE]], implicit $exec
   ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
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rampitec wrote:
> Why did it change? This is unexpected.
These are the only changes to the tablegen record.
field bit VOPC = 0; -> field bit VOPC = 1;
bits<64> TSFlags (VOPC bit is now set)

There is no difference in the SIFixSGPRCopies output. It seems to me as if when the instruction is being constructed it is now commuted. Since this instruction should commute, do you think this is a bad change? 



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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126989/new/

https://reviews.llvm.org/D126989