[llvm] cbbc7e4 - llvm-reduce: Don't set generic instruction operands to undef

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-06-07T10:28:23-04:00
New Revision: cbbc7e4a7572db4a3ddc008a64f22893220296ef

URL: https://github.com/llvm/llvm-project/commit/cbbc7e4a7572db4a3ddc008a64f22893220296ef
DIFF: https://github.com/llvm/llvm-project/commit/cbbc7e4a7572db4a3ddc008a64f22893220296ef.diff

LOG: llvm-reduce: Don't set generic instruction operands to undef

The intention is that these should never have undef operands. It turns
out the restriction the verifier enforces is too lax. The verifier
enforces that registers without a register class cannot be undef, but
it's valid to use a register with a register class and type. The
verifier needs to change to be based on the opcode.

Added: 
    llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir

Modified: 
    llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
    llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/tools/llvm-reduce/mir/generic-vreg.mir b/llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
index 1b705e0a7e51..2bc78b34bed7 100644
--- a/llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
+++ b/llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
@@ -1,5 +1,5 @@
 # REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce -abort-on-invalid-reduction -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
 
 # Verify that reduction works with generic virtual registers, and the

diff  --git a/llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir b/llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
new file mode 100644
index 000000000000..6bcad29d46ab
--- /dev/null
+++ b/llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
@@ -0,0 +1,25 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# Generic instructions should not have undef set on operands
+# CHECK-INTERESTINGNESS: G_ADD
+
+# RESULT: %1:vreg_64(s64) = IMPLICIT_DEF
+# RESULT: %add:_(s64) = G_ADD %1, %1
+
+---
+name: func
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
+
+    %0:vgpr(s32) = G_IMPLICIT_DEF
+    %1:vreg_64(s64) = IMPLICIT_DEF
+    %add:_(s64) = G_ADD %1, %1
+    %ptr:_(p1) = G_IMPLICIT_DEF
+    G_STORE %0(s32), %ptr(p1) :: (store (s32), addrspace 1)
+    S_ENDPGM 0, implicit %add(s64), implicit %1(s64)
+
+...

diff  --git a/llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp b/llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp
index 1db50ea66329..a461cb8e5527 100644
--- a/llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp
+++ b/llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp
@@ -22,6 +22,10 @@ static void removeUsesFromFunction(Oracle &O, MachineFunction &MF) {
 
   for (MachineBasicBlock &MBB : MF) {
     for (MachineInstr &MI : MBB) {
+      // Generic instructions are not supposed to have undef operands.
+      if (isPreISelGenericOpcode(MI.getOpcode()))
+        continue;
+
       int NumOperands = MI.getNumOperands();
       int NumRequiredOps = MI.getNumExplicitOperands() +
                            MI.getDesc().getNumImplicitDefs() +