[llvm] 81edc83 - [AMDGPU] Add support for the .reloc directive
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 7 07:27:11 PDT 2022
Author: Jay Foad
Date: 2022-06-07T15:18:54+01:00
New Revision: 81edc831fb90c289eb0616bae3658e4feea9a99c
URL: https://github.com/llvm/llvm-project/commit/81edc831fb90c289eb0616bae3658e4feea9a99c
DIFF: https://github.com/llvm/llvm-project/commit/81edc831fb90c289eb0616bae3658e4feea9a99c.diff
LOG: [AMDGPU] Add support for the .reloc directive
Differential Revision: https://reviews.llvm.org/D127117
Added:
llvm/test/MC/AMDGPU/reloc-directive.s
Modified:
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
index 32d771e276286..f02e7fb195582 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -50,7 +50,10 @@ class AMDGPUAsmBackend : public MCAsmBackend {
bool writeNopData(raw_ostream &OS, uint64_t Count,
const MCSubtargetInfo *STI) const override;
+ Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
+ bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
+ const MCValue &Target) override;
};
} //End anonymous namespace
@@ -137,6 +140,9 @@ void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
MutableArrayRef<char> Data, uint64_t Value,
bool IsResolved,
const MCSubtargetInfo *STI) const {
+ if (Fixup.getKind() >= FirstLiteralRelocationKind)
+ return;
+
Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
if (!Value)
return; // Doesn't change encoding.
@@ -156,6 +162,15 @@ void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
}
+Optional<MCFixupKind> AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
+ return StringSwitch<Optional<MCFixupKind>>(Name)
+#define ELF_RELOC(Name, Value) \
+ .Case(#Name, MCFixupKind(FirstLiteralRelocationKind + Value))
+#include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
+#undef ELF_RELOC
+ .Default(None);
+}
+
const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
@@ -163,12 +178,21 @@ const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
{ "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
};
+ if (Kind >= FirstLiteralRelocationKind)
+ return MCAsmBackend::getFixupKindInfo(FK_NONE);
+
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
return Infos[Kind - FirstTargetFixupKind];
}
+bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &,
+ const MCFixup &Fixup,
+ const MCValue &) {
+ return Fixup.getKind() >= FirstLiteralRelocationKind;
+}
+
unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
return 4;
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
index bb2c298c28503..066b36622a16b 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -65,7 +65,10 @@ unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_AMDGPU_REL64;
}
- switch (Fixup.getKind()) {
+ MCFixupKind Kind = Fixup.getKind();
+ if (Kind >= FirstLiteralRelocationKind)
+ return Kind - FirstLiteralRelocationKind;
+ switch (Kind) {
default: break;
case FK_PCRel_4:
return ELF::R_AMDGPU_REL32;
diff --git a/llvm/test/MC/AMDGPU/reloc-directive.s b/llvm/test/MC/AMDGPU/reloc-directive.s
new file mode 100644
index 0000000000000..351a5c956295c
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/reloc-directive.s
@@ -0,0 +1,64 @@
+# RUN: llvm-mc -triple=amdgcn--amdhsa %s | FileCheck --check-prefix=PRINT %s
+
+# RUN: llvm-mc -filetype=obj -triple=amdgcn--amdhsa %s -o %t
+# RUN: llvm-readobj -r %t | FileCheck %s
+
+# PRINT: .reloc 2, R_AMDGPU_NONE, .data
+# PRINT-NEXT: .reloc 1, R_AMDGPU_NONE, foo+4
+# PRINT-NEXT: .reloc 0, R_AMDGPU_NONE, 8
+# PRINT-NEXT: .reloc 0, R_AMDGPU_ABS32_LO, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_ABS32_HI, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_ABS64, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL32, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL64, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_ABS32, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_GOTPCREL, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_GOTPCREL32_LO, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_GOTPCREL32_HI, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL32_LO, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL32_HI, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_RELATIVE64, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL16, .data
+
+# CHECK: 0x2 R_AMDGPU_NONE .data
+# CHECK-NEXT: 0x1 R_AMDGPU_NONE foo 0x4
+# CHECK-NEXT: 0x0 R_AMDGPU_NONE - 0x8
+# CHECK-NEXT: 0x0 R_AMDGPU_ABS32_LO .data
+# CHECK-NEXT: 0x0 R_AMDGPU_ABS32_HI .data
+# CHECK-NEXT: 0x0 R_AMDGPU_ABS64 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL32 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL64 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_ABS32 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_GOTPCREL .data
+# CHECK-NEXT: 0x0 R_AMDGPU_GOTPCREL32_LO .data
+# CHECK-NEXT: 0x0 R_AMDGPU_GOTPCREL32_HI .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL32_LO .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL32_HI .data
+# CHECK-NEXT: 0x0 R_AMDGPU_RELATIVE64 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL16 .data
+
+.text
+ s_nop 0
+ s_nop 0
+ .reloc 2, R_AMDGPU_NONE, .data
+ .reloc 1, R_AMDGPU_NONE, foo+4
+ .reloc 0, R_AMDGPU_NONE, 8
+ .reloc 0, R_AMDGPU_ABS32_LO, .data
+ .reloc 0, R_AMDGPU_ABS32_HI, .data
+ .reloc 0, R_AMDGPU_ABS64, .data
+ .reloc 0, R_AMDGPU_REL32, .data
+ .reloc 0, R_AMDGPU_REL64, .data
+ .reloc 0, R_AMDGPU_ABS32, .data
+ .reloc 0, R_AMDGPU_GOTPCREL, .data
+ .reloc 0, R_AMDGPU_GOTPCREL32_LO, .data
+ .reloc 0, R_AMDGPU_GOTPCREL32_HI, .data
+ .reloc 0, R_AMDGPU_REL32_LO, .data
+ .reloc 0, R_AMDGPU_REL32_HI, .data
+ .reloc 0, R_AMDGPU_RELATIVE64, .data
+ .reloc 0, R_AMDGPU_REL16, .data
+
+.data
+.globl foo
+foo:
+ .long 0
+ .long 0
More information about the llvm-commits
mailing list