[llvm] e6723d8 - llvm-reduce: Fix crashes on unreachable blocks for MIR instructions

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-06-07T10:00:26-04:00
New Revision: e6723d80c7518c3d7a5422952fe963d8d125f99d

URL: https://github.com/llvm/llvm-project/commit/e6723d80c7518c3d7a5422952fe963d8d125f99d
DIFF: https://github.com/llvm/llvm-project/commit/e6723d80c7518c3d7a5422952fe963d8d125f99d.diff

LOG: llvm-reduce: Fix crashes on unreachable blocks for MIR instructions

Added: 
    llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir

Modified: 
    llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir b/llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
new file mode 100644
index 0000000000000..32abcf14f14d8
--- /dev/null
+++ b/llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
@@ -0,0 +1,43 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -simplify-mir -mtriple=amdgcn-amd-amdhsa --delta-passes=instructions --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# Make sure there's no crash with unreachable blocks.
+
+# CHECK-INTERESTINGNESS: S_NOP
+
+# RESULT: bb.0:
+
+# RESULT: %3:vgpr_32 = IMPLICIT_DEF
+# RESULT-NEXT: %4:sreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %5:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+# RESULT-NEXT: S_BRANCH %bb.3
+
+# RESULT: bb.1:
+# RESULT-NEXT: S_BRANCH %bb.3
+
+# RESULT: bb.2:
+# RESULT-NEXT: S_NOP 0, implicit %3, implicit killed %5, implicit %4
+
+---
+name: unreachable_block
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+    S_BRANCH %bb.3
+
+  bb.1:
+    %1:sreg_64 = S_MOV_B64 0
+    S_BRANCH %bb.3
+
+  bb.2:
+    %2:vreg_64 = IMPLICIT_DEF
+    S_NOP 0, implicit %0, implicit killed %2, implicit %1
+    S_BRANCH %bb.3
+
+  bb.3:
+
+...

diff  --git a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
index f5f74f1bb4d6e..c87d5eb9a44f2 100644
--- a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
+++ b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
@@ -106,14 +106,17 @@ static void extractInstrFromFunction(Oracle &O, MachineFunction &MF) {
         MachineBasicBlock::reverse_iterator RI(*MI);
         MachineBasicBlock *BB = MI->getParent();
         ++RI;
-        while (NewReg == 0 && BB) {
-          NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, RegTy, ToDelete);
-          // Prepare for idom(BB).
-          if (auto *IDM = MDT.getNode(BB)->getIDom()) {
-            BB = IDM->getBlock();
-            RI = BB->rbegin();
-          } else {
-            BB = nullptr;
+
+        if (MDT.isReachableFromEntry(BB)) {
+          while (NewReg == 0 && BB) {
+            NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, RegTy, ToDelete);
+            // Prepare for idom(BB).
+            if (auto *IDM = MDT.getNode(BB)->getIDom()) {
+              BB = IDM->getBlock();
+              RI = BB->rbegin();
+            } else {
+              BB = nullptr;
+            }
           }
         }
       }