[PATCH] D127203: [LoongArch 3/n] Add codegen support for the bitwise binary operations and part of other operations

[Lu Weining via Phabricator via llvm-commits]

SixWeining created this revision.
SixWeining added reviewers: MaskRay, xry111, xen0n, wangleiat, rengolin, myhsu.
Herald added subscribers: luke957, StephenFan, s.egerton, simoncook, hiraditya.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added subscribers: llvm-commits, pcwang-thead.
Herald added a project: LLVM.

Reference:
https://llvm.org/docs/LangRef.html#bitwise-binary-operations
https://llvm.org/docs/LangRef.html#other-operations

The reason why other operations are implemented here is that some
bitwise binary operations depend on them. For example, on loongarch32,
`shl` over i64 data requires `select`.

Depends on D127200 <https://reviews.llvm.org/D127200>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127203

Files:
  llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
  llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
  llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/ashr.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-flt.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/icmp.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/lshr.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-dbl.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-flt.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-int.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-dbl.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-flt.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-int.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-dbl.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-flt.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-int.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/shl.ll
  llvm/test/CodeGen/LoongArch/ir-instruction/xor.ll
  llvm/test/CodeGen/LoongArch/shift-masked-shamt.ll

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